Method for testing ECC logic

Details Method for testing ECC logic Method for testing ECC logic

1993-09-20

1996-03-26

Voeltz, Emanuel T.

Excavating

371 3, 371 221, H03M 1300

Patent

active

055027326

ABSTRACT:
A system and method for checking the test logic contained in a computer memory system during POST such that any errors can be determined and made available to the system software prior to beginning processing operations. Single and double bit errors are induced which the ECC logic must identify and correct. The CPU compares the data that is written to memory with the data that is read back. Thus, since it is known that an error occurred, due to the induced error provided by the present invention, identical data will verify that the ECC correction logic is working properly. More specifically, a multiplexer is provided in the data write path which substitutes a constant set of identical bits for the actual data generated by the CPU. ECC bits are generated based on the actual generated test data, rather than the inserted identical bits. The substituted data bits and generated ECC bits are then stored in memory. An error condition is identified when the data and ECC code is read back from memory. The correction logic then corrects the data, in the case of a single bit error, such that the data read by the CPU is the same as the originally generated data.

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