Excavating
Patent
1996-10-10
1997-09-02
Canney, Vincent P.
Excavating
G06F 1100
Patent
active
056639643
DESCRIPTION:
BRIEF SUMMARY
The invention concerns a method for testing digital memory devices, in which device, the quantity of selectable numerical values being defined by the number of memory cell locations, and the assignment of the numerical values occurring in such a way that a conclusion as to the address of the memory cells can be drawn from a numerical sequence from a plurality of memory cells succeeding one another in the address field; memory device are written to them; the respective assigned numerical value; and identical, an error message is generated.
A method of this kind is known from IMB TECHNICAL DISCLOSURE BULLETIN Vol. 32, No. 1, June 1989, New York, USA, page 220: "Method for address fault detection." In this method, two numbers are used to check a memory with four 1-bit wide memory cells; one of the numbers 0 or 1 is assigned to each memory cell, and from the sequence of assigned numbers of a plurality of memory cells succeeding one another in the address field, a conclusion can be drawn as to the address of the memory cell. The assigned numbers are written into the respective memory cell, all four memory cells of the overall memory being written to in succession, beginning with the memory cell with the lowest address up to the memory cell with the highest address. The memory cells are then read out, and the memory contents compared with the respective assigned number. A difference between the read-out memory contents and the assigned number may be attributed to an addressing or memorization error. The assigned numbers are then stored again, this time beginning with the highest address. The memory cells are then read out again, and the memory contents compared with the assigned number to check identity.
In another known method, the digital memory device test occurs in such a way that the address of each memory cell is written into that cell, and then the memory is read out again. Any errors which occur can be detected by comparing the respective stored address with the read-out memory contents, which must correspond to that address. Because of the high memory capacity of many circuits, this is a complex procedure.
In printed circuit boards, the most common embodiment of modern circuits, short circuits occur particularly often between adjacent conductor paths. In the case of memories arranged on circuit boards, this often causes addressing errors to occur, i.e. the data are written into incorrect memory cells or multiple accesses occur to individual memory cells under various addresses. Addressing errors of this kind are not always detectable with the memory test just cited.
It is the object of the invention to indicate a method with which, in digital memory devices with memory cells comprising a plurality of address bits, the aforesaid addressing errors can be recognized. According to the invention this is done, in a method of the aforesaid kind, by the fact that in a digital memory device with memory cells each comprising four address bits, the assignment of the numerical values to the memory cells occurs as defined by
The invention will be explained in more detail with reference to two Figures, which show by way of example:
in FIG. 1, an ordinary electronic circuit; and
in FIG. 2, the coding of test data.
The electronic circuit depicted in FIG. 1 comprises a memory 1 and a microprocessor 2. The connection between the two functional groups is constituted by a bus system consisting of an address bus A with four data lines and a data bus D with two data lines.
The two data lines correspond to the width of one two-bit memory location. The entire memory possesses 2.sup.4 =16 different memory cells. It not possible to unequivocally code these 16 different memory cells with only the two data lines with a total of four displayable states.
In conventional test methods, therefore, only a portion of the address information is written into the memory cells, for example the two lowest-order address bits. With this test method, however, addressing errors that occur because of a short circuit of the top two address lines ar
REFERENCES:
patent: 4061908 (1977-12-01), de Jonge et al.
"Method for Address Fault Detection", IBM Technical Disclosure Bulletin, vol. 32, No. 1, Jun. 1989, New York.
"Nonvolatile Ram Failure Rate Detection Through the Use of Redundancy", IBM Technical Disclosure Bulletin, vol. 31, No. 10, Mar. 1989, New York.
Canney Vincent P.
Siemens Aktiengesellschaft
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