Method for testing cache memory systems

Details Method for testing cache memory systems Method for testing cache memory systems

1996-06-17

1998-11-03

Beausoliel, Jr., Robert W.

Excavating

39518318, G06F 1100

Patent

active

058319875

ABSTRACT:
A method for testing cache memory components of a computer system. The method tests RAM by detecting whether external memory caching can be disabled via software, and if not, the RAM is tested in segments large enough to ensure overflow of the primary L1 and secondary L2 CPU cache memory. The size of the L1 and L2 cache memories are measured by timing memory access speeds in Kb/Sec of successively larger blocks of memory. Additionally, a method for testing a particular region of system memory is provided, even if the memory region is in use by the operating system, which is accomplished by creating an isolated environment that switches the operating system off and on for each pass of the memory test.

REFERENCES:
patent: 5497458 (1996-03-01), Finch et al.
patent: 5511180 (1996-04-01), Schieve
patent: 5513344 (1996-04-01), Nakamura
patent: 5524208 (1996-06-01), Finch et al.

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