Patent
1996-10-15
1999-08-24
Teska, Kevin J.
G06F 1120
Patent
active
059434856
ABSTRACT:
In a method for generating a mapping of logical addresses to a layout of an electronic circuit structure first and second relations are established. The first relation is representative of the mapping of signal pairs to the layout and the second relation is representative of the mapping of the logical addresses to the signal pairs. Joining of the first and second relations yields a mapping table which can be used for purposes of circuit testing and design.
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Bracha Gabriel
Weisberger Eytan
Atkins Robert D.
Do Thuan
Handy Bob
Motorola Inc.
Teska Kevin J.
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