Method for testing and diagnosing MOS transistors

Details Method for testing and diagnosing MOS transistors Method for testing and diagnosing MOS transistors

1999-10-04

2001-08-14

Karlsen, Ernest (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S762010

Reexamination Certificate

active

06275059

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the field of testing and diagnosing MOS transistors and MOS transistor fabrication and design.
2. Description of the Related Art
A direct-current current-voltage (DCIV) measurement technique of interface and oxide traps on oxidized silicon is demonstrated. The technique uses the gate-controlled parasitic bipolar junction transistor of a metal-oxide-silicon field-effect transistor in a p
junction isolation well to monitor the change of the oxide and interface trap density. The debase and collector currents are the monitors, hence, this technique is more sensitive and reliable than the traditional ac methods for determination of fundamental kinetic rates and transistor degradation mechanisms, such as charge pumping.
It is well recognized that the electrical characteristics of metal-oxide-semiconductor transistors (MOST's) and bipolar junction transistors (BJT's) degrade during circuit operation due to channel-hot-electron (CHE) and substrate-hot-electron (SHE) stresses which increase oxide (Q
OT
) and interface trap (Q
IT
) densities [1], [2]
1
. In MOST's , the trapped charges reduce the mobility (&Dgr;&mgr;) and shift the threshold gate voltage (&Dgr;V
GT
), both of which reduce drain saturation current (&Dgr;I
D
) which slows down the switching speed due to longer charging time of interconnect or load capacitances at lower currents. The trapped charges also shift the subthreshold gate voltage (&Dgr;V
GT-sub
), and decrease subthreshold slope of the drain-current versus gate-voltage curve, which reduces the current cut-off sharpness, thereby increasing leakage current or standby power and decreasing the noise margin. In BJT's , Q
IT
and Q
OT
will increase the minority carrier recombination rate in the base, thereby reducing its current gain, such as the common-emitter current gain, &bgr;
F
[3]. Thus, a quantative separation of the effects of Q
OT
and Q
IT
is necessary to delineate the location and physical origin of the degradation in order to design and manufacture highly reliable integrated circuits with ten-year or longer operating life.
The separation of Q
OT
and Q
IT
is generally difficult. It has not been reliably separated using the traditional capacitance and conductance methods or the transient methods because the test structures are two-terminal capacitors, or very small test transistors which give extremely small capacitances due to the very small device area. Many traditional methods for separating Q
OT
and Q
IT
were reviewed [4], and a two-step method was demonstrated. However, it uses the subthreshold slope to monitor Q
IT
which is reliable only when there is not an inhomogeneous or lateral distribution of Q
IT
and Q
OT
. Hence, it is not reliable for monitoring the highly nonuniform Q
IT
and Q
OT
generated by CHE stress.
A novel method is demonstrated in this paper which measures the de base and collector currents versus the gate voltage, to be known as DCIV method (in analogy to the traditional usage such as HFCV for high-frequency capacitance-voltage or QSCV for quasi-static CV), to monitor the Q
IT
and Q
OT
. The novel DCIV method contains two features: 1) The base current (I
B
) of the vertical BJT is used to measure the recombination current at the interface traps generated during fabrication or operation which avoids the error from lateral distribution or areal nonuniformity of Q
IT
and Q
OT
because I
B
is directly proportional to N
IT
or Q
IT
/q. 2) The Collector current (I
C
) of the vertical BJT is used to measure the Q
OT
because I
C
increases sharply when the gate voltage passes the flat-band value toward depletion and inversion. The method will be described in this article using the nMOST and npnBJT of the BiMOS structure shown in FIG.
1
. This BiMOS structure has been used previously to fabricate large test transistors wish nearly 400,000 &mgr;m
2
gate oxide area by Thompson ([8] and [9] cited in [4]), but it is also present in the submicrometer nMOST's in a p-well on n-substrate of production CMOS (Complementary MOS) inverter circuits. Thus, the novel DCIV method to be described can be easily applied to production test transistors and some examples to be given were data measured on micrometer and submicrometer MOST-BIT production structures.
With reference to
FIG. 1
, the BIT can be measured before and after a stress in two configurations: The top-emitter (top-E) or bottom-emitter (bottom-E) measurement configurations, with the n+drain/p-base or n+substrate
-epitaxy/p-base as the forward biased emitter/base junction. Our geometrical terminology deviates from the traditional, emitter-up and emitter-down, which confuses the geometrical location of the emitter with the emitted-charge flow direction. In both configurations, the shape of the I
B
−V
GB
curve and the magnitude of I
B
at a constant V
EB
will measure Q
IT
[5], [6]. However, we recently anticipated that the shape and magnitude of I
C
will also be a strong function of V
GB
in both configurations because I
C
increases sharply at the flat-band gate voltage, V
GB-flatband
, from a low constant current t a high constant current at strong inversion voltage V
GB-threshold
. This sharp increase occurs when the electron-channel between the n+drain and n+drain and n+source appears at V
GB-flatband
which abruptly increases the emitter/base area in the top-E configuration and the collector/base area in the bottom-E configuration.
The stress-induced base current, &Dgr;I
B
, is solely due to electron-hole recombination at the stress-generated interface traps [5], [6], hence, is a function of stress-induced interface charge and trap concentrations, &Dgr;Q
IT
and &Dgr;N
IT
, to the stress-induced density-of-states of the interface traps and surface recombination velocity, &Dgr;D
IT
and &Dgr;S
Q
. However, the increase of the collector current with V
GB
is nearly all from geometrical increase in the emitter or collector area contributed from the nMOST's electron channel. Therefore; the lateral shift in the I
C
−V
GB
curve, &Dgr;V-GB, is mainly a function of the stress-induced change of flatband gate voltage, &Dgr;V
GB-flatband+
and hence is a very sensitive monitor of &Dgr;Q
QT
+&Dgr;Q
IT
. Thus, combining the &Dgr;I
B
−V
GB
and I
C
−V
GB
data will enable the separation of &Dgr;Q
OT
and &Dgr;Q
IT
. Experimental data in the following section will demonstrate this capability of the novel DCIV method.
Minority carrier surface recombination rate or velocity S
o
at the Si/SiQ
2
interface was studied extensively since the use of MOS-gate-controlled BJT was demonstrated by one of us in 1961-1962 [5], [6]. In the early and follow-up experiments, I
B
was measured in either the top-emitter configuration [5]-[9] or bottom-emitter configuration [10]-[13], to evaluate S
O
. In [7] through [9], the BJT &bgr;
F
degradation during emitter-base reverse-bias stress at the junction breakdown voltage was also studied. In many of these earlier measurements, the I
B
−V
GB
curve was also displaced along the gate-voltage axis due to stress, but the peak in I
B
−V
GB
was not very sharp. In some cases no peak was observed. In addition, the magnitude of I
B
was greatly increased by the generated N
IT
. Thus, an estimate of &Dgr;Q
OT
from the shift of V
GB
at the peak &Dgr;I
B
in the &Dgr;I
B
−V
GB
curve cannot be very accurate and reliable.
Production n-channel MOST fabricated by state-of-the-art CMOS process is measured to demonstrate the proposed DCIV method. The starting n-Si wafer has a p-base well with surface concentration of 1×10
16
cm
−3
, gate oxide thickness of x
O
≅150 Å. channel length L=1.6 &mgr;m, and the gate area of A
G
=1.6×100 &mgr;m
2
. The cross-secti

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