Excavating
Patent
1995-09-05
1997-10-21
Beausoliel, Jr., Robert W.
Excavating
371 212, 365201, G11C 2900
Patent
active
056805446
ABSTRACT:
A test system is provided which tests the on chip cache of a microprocessor (CPU). The test system provides test vectors to the CPU in a specified sequences. The CPU then uses its internal general purpose registers to write the vectors the cache memory locations. After writing, the data is read back and compared to an expected value. The results are then stored in other general purpose registers of the CPU. Using the CPUs general purpose registers to record the test results allows the test system to test many cache locations in parallel. Furthermore the test system allows the test to proceed in a fixed number of CPU clock cycles regardless of any detected errors.
REFERENCES:
patent: Re34445 (1993-11-01), Hayes et al.
patent: 5195096 (1993-03-01), Moore
patent: 5305327 (1994-04-01), Huckstepp
patent: 5471480 (1995-11-01), You
patent: 5513344 (1996-04-01), Nakamura
patent: 5539878 (1996-07-01), Kikinis
patent: 5555249 (1996-09-01), Hiley et al.
Edmondson John
Taylor Scott
Beausoliel, Jr. Robert W.
De'cady Albert
Digital Equipment Corporation
Fisher Arthur W.
Pappas Joanne N.
LandOfFree
Method for testing an on-chip cache for repair does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for testing an on-chip cache for repair, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for testing an on-chip cache for repair will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1014161