Method for testing an integrated circuit means having a hierarch

Details Method for testing an integrated circuit means having a hierarch Method for testing an integrated circuit means having a hierarch

1993-02-16

1995-12-19

Baker, Stephen M.

Excavating

371 221, G01R 31317, G01R 313185

Patent

active

054775485

ABSTRACT:
A method for testing a hierarchically organized integrated circuit means first attacks each assembly in sequence thereof, and in each assembly executing an assembly test cycle. Each assembly test cycle within the assembly in question attacks each macro thereof in sequence and conditionally executes therein a test run under selective control of a macro test mode (MTM) signal. The number of hierarchy levels may be other than three. The method may be applicable to separate integrated circuits or to a wired board with a plurality of circuits.

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