Method for testing an electrically erasable and programmable mem

Details Method for testing an electrically erasable and programmable mem Method for testing an electrically erasable and programmable mem

1995-06-07

1996-12-31

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518509, 36518529, 365200, 365201, G11C 700

Patent

active

055900755

ABSTRACT:
A method for testing an electrically erasable and programmable memory device comprising a matrix of memory cells and redundancy memory cells for functionally substituting defective memory cells, comprises the steps of: programing all the memory cells of the memory device; submitting all the memory cells of the memory device to a preliminary electrical erasure for a time much shorter than an average erasing time of the memory cells; reading the information stored in all the memory cells of the memory device; memorizing the addresses of defective memory cells which have been read as erased memory cell; storing the addresses of the defective memory cells in redundancy registers associated to redundancy memory cells which must substitute the defective memory cells.

REFERENCES:
patent: 4733394 (1988-03-01), Giebel
patent: 4963825 (1990-10-01), Mielke
patent: 5023874 (1991-06-01), Houston
patent: 5053990 (1991-10-01), Kreifels et al.
patent: 5400286 (1995-03-01), Chu et al.
patent: 5410511 (1995-04-01), Michiyama
Vancu et al., "A 30 ns Fault Tolerant 16K CMOS EEPROM," in IEEE Solid-State Circuits Conference, vol. 31, New York, NY, Feb. 17-19, 1988, pp. 128 and 328.

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