Method for synthesizing a sequential circuit

Details Method for synthesizing a sequential circuit Method for synthesizing a sequential circuit

1995-12-29

1998-03-24

Chin, Gary

Boots, shoes, and leggings

364488, 364490, 364491, G06F 1750, G06F 1710, G06F 1500

Patent

active

057319839

ABSTRACT:
A method of circuit synthesis which considers all circuit configurations that can be designed utilizing a retiming with logic duplication (RLD) methodology. These circuit configurations (RLD configurations) each have significantly different area, performance and testability characteristics and are represented as a set of feasible solutions to an integer linear program (ILP). The ILP permits the evaluation of different design and testability metrics for each of the configurations. An approach to solve several useful special cases of the ILP in polynomial time and an application of RLD transformation to partial scan is shown. Using this method, a desired RLD configuration is produced having a minimal number of duplicated logic nodes.

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