Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2005-09-21
2010-10-19
Shah, Kamini S (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S003000
Reexamination Certificate
active
07818158
ABSTRACT:
In a computer simulation of an analog device in a digital circuit, a piece-wise linear lookup table is used to determine the channel resistance of the transistors in the analog device, allowing the node voltages to take on non-digital values. The piece-wise linear lookup table contains a set of channel resistances corresponding respectively to gate-to-source voltages. The program uses multi-terminal binary decision graphs (MTBDDs) to represent non-digital resistances, capacitances and voltages in the circuit as a function of symbolic inputs. The program can analyze circuits containing more than two voltage sources by modeling voltage sources with voltage dividers between the maximum and minimum voltages in the circuit.
REFERENCES:
patent: 5264785 (1993-11-01), Greason
patent: 5313398 (1994-05-01), Rohrer et al.
patent: 5373457 (1994-12-01), George et al.
patent: 5553008 (1996-09-01), Huang et al.
patent: 5675502 (1997-10-01), Cox
patent: 5686863 (1997-11-01), Whiteside
patent: 5687355 (1997-11-01), Joardar et al.
patent: 5692158 (1997-11-01), Degeneff et al.
patent: 5999718 (1999-12-01), Wang et al.
patent: 6134513 (2000-10-01), Gopal
patent: 6190433 (2001-02-01), Van Fleet et al.
patent: 6269277 (2001-07-01), Hershenson et al.
patent: 6459324 (2002-10-01), Neacsu et al.
patent: 6577992 (2003-06-01), Tcherniaev et al.
patent: 6634012 (2003-10-01), Zhong et al.
patent: 6662149 (2003-12-01), Devgan et al.
patent: 6807520 (2004-10-01), Zhou et al.
patent: 7006961 (2006-02-01), Mandell et al.
patent: 7013253 (2006-03-01), Cong et al.
patent: 7049875 (2006-05-01), Tsividis
patent: 7143021 (2006-11-01), McGaughy et al.
patent: 7353157 (2008-04-01), Wasynczuk et al.
patent: 2001/0029601 (2001-10-01), Kimura et al.
patent: 2002/0016704 (2002-02-01), Blanks
patent: 2003/0120473 (2003-06-01), Jain et al.
patent: 2003/0208347 (2003-11-01), Huang
patent: 2004/0049370 (2004-03-01), Stanley et al.
patent: 2004/0117162 (2004-06-01), Ozis et al.
patent: 2004/0148150 (2004-07-01), Ashar et al.
patent: 2005/0027491 (2005-02-01), Fertner et al.
patent: 2005/0143966 (2005-06-01), McGaughy
patent: 2005/0149311 (2005-07-01), McGaughy
patent: 2005/0149312 (2005-07-01), McGaughy
patent: 2005/0257178 (2005-11-01), Daems et al.
patent: 2005/0273307 (2005-12-01), Hemmett
patent: 2006/0069537 (2006-03-01), Cao
patent: 2007/0261015 (2007-11-01), Morgenshtein et al.
patent: 2008/0033708 (2008-02-01), Kanapka et al.
Understanding Semiconductor Devices by Sima Dimitrijev ISBN 0-19-513186-X Publication year 2000 p. 4-5.
An amorphous-silicon thin-film transistor model including variable resistance effect by Tanizawa, M.; Kikuta, S.; Nakagawa, N.; Ishikawa, K.; Kotani, N.; Miyoshi, H.;Simulation of Semiconductor Processes and Devices, 1996. SISPAD 96. 1996 International Conference onSep. 2-4, 1996 pp. 181-182.
Computing Logic-Stage Delays Using Circuit Simulation and Symbolic Elmore Analysis by Clayton B. McDonald Randal E. Bryant; IEEE 2001 p. 283-288.
TETA: Transistor-Level Engine for Timing Analysis by F. Dartu and L. T. Pileggi. Proceedings of the Design Automation by Conference, pp. 595-598, Jun. 1998.
Microelectronic Circuits- Fourth Edition ; Sedra and Smith Jan. 1998; ISBN 0-19-511663-1; p. 366-369 and book cover.
Bahar, R. I. et al. “Algebraic Decision Diagrams And Their Applications”, ACM/IEEE International Conference on Computer Aided Design, Nov. 1993, pp. 4.
Somenzi, F. “CUDD: CU Decision Diagram Package—Release 2.2.0”, May 12, 1998, pp. 47.
Bryant, R. E. “Graph-Based Algorithms For Boolean Function Manipulation”, IEEE Transactions on Computers, vol. C-35, No. 8, Aug. 1986, pp. 25.
Andersen, H. R. et al. “Boolean Expression Diagrams”, In LICS, 1997, pp. 21.
Kuehlmann, A. et al. “Equivalence Checking Using Cuts And Heaps”, Proceedings of the Design Automation Conference (DAC'97), Anaheim, CA, Jun. 1997, pp. 6.
Bryant, R. E. et al. “Verification Of Arithmetic Circuits Using Binary Moment Diagrams”, Software Tools for Technology Transfer, Springer-Verlag, vol. 3, No. 2, May 2001, pp. 18.
Chen, Y.-A. et al. “PHDD: An Efficient Graph Representation For Floating Point Circuit Verification”, International Conference on Computer-Aided Design (ICCAD'97), Nov. 1997, pp. 6.
PhD Thesis titled “Symbolic Functional and Timing Verification of Transistor Level Circuits,” Clayton B. McDonald, Apr. 9, 2001, Carnegie-Mellon University, 91 pages.
Chou Hsinwei
Gupta Smriti
McDonald Clayton B.
Saxena Akesh
Shah Kamini S
Silicon Valley Patent & Group LLP
Suryadevara Omkar
Synopsys Inc.
LandOfFree
Method for symbolic simulation of circuits having... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for symbolic simulation of circuits having..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for symbolic simulation of circuits having... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4162422