Semiconductor device manufacturing: process – Making regenerative-type switching device – Having field effect structure
Reexamination Certificate
2000-01-26
2001-06-19
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making regenerative-type switching device
Having field effect structure
C438S268000, C438S279000
Reexamination Certificate
active
06248616
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to junction-isolating integrated circuits and, more particularly, to a method and a device for suppressing parasitic effects in an integrated circuit.
BACKGROUND OF THE INVENTION
In junction-isolated integrated circuits, transient biasing conditions can occur during operation such as to cause the passage of unwanted currents in the substrate of the integrated circuit and within the regions thereof isolated from one another by reverse biased p-n junctions. These currents are due to parasitic transistors becoming conductive. The transient biasing conditions mainly occur upon commutation of inductive loads, such as inductances and motors, or capacitive loads, such as capacitors, batteries and accumulators, effected by means of electronic switches of the integrated circuit.
A typical example of integrated circuit in which parasitic effects of this type occur is a driver circuit for inductive loads, for example, a transistor bridge. Such a circuit is shown in
FIG. 1
connected between terminals, indicated +Vcc and the ground symbol, of a dc supply voltage source, which controls a motor M. In this example the transistors, indicated M
1
-M
4
are power transistors of DMOS type, that is, double diffusion MOS field-effect transistors. Each of these transistors has a diode Db
1
-Db
4
intrinsic in its structure, and which acts as a recovery diode. However, a bipolar transistor bridge with reversed diodes between the emitter and collector terminals could be used equally well to describe the parasitic phenomena caused in the integrated circuit by the switching of the inductive load.
As is known, a transistor bridge circuit is controlled in such a way that the transistors in the diagonals of the bridge are alternatively conductive and switched off so that currents in opposite senses are applied successively to the load. The parasitic effects described above occur during switching. Consider, for example, the instant at which the conduction of the transistors M
1
and M
2
is interrupted before activation of the transistors M
3
and M
4
. In these conditions the energy stored in the inductive load M causes overvoltage in both senses on the output terminals of the bridge to which the load is connected. In particular, the source terminal S of the transistor M
2
goes to a voltage greater than that of the supply voltage Vcc and the drain terminal D of the transistor of M
1
goes to a lower voltage than ground so that the recovery diodes Db
1
and Db
2
associated with the transistors M
1
and M
2
both become conductive.
The effects of the positive overcurrent on the source terminal of M
2
are described in relation to FIG.
2
. The transistor M
2
is formed on a substrate
10
of monocrystalline silicon doped with impurities of p-type, namely in a region
11
doped with n-type impurities delimited by a major or frontal surface of the substrate
10
, a buried region
12
strongly doped with n-type impurities and therefore indicated n+, and an isolation region
13
strongly doped with p-type impurities, therefore indicated p+. The buried region
12
and the isolation region
13
form, with the substrate
10
and the region
11
respectively, a pn junction which, in normal operation of the integrated circuit, is reversed biased and electrically isolates the region
11
from the substrate
10
. The region
11
provides the drain region of the transistor and has, on a frontal surface, a region
14
strongly doped with n-type impurities and a first metal contact electrode
14
′ which provides the drain terminal D. A p-type region
15
is formed within the n-type region
11
and provides the body region of the transistor.
A region
9
strongly doped with n-type impurities is formed within the body region
15
and provides the source region of the transistor. A second metal contact electrode
16
is formed on the frontal surface in contact with the source and body regions and constitutes the source terminal S. The source region
15
delimits a channel
17
with the edges of the body region
15
. The channel
17
is overlain by a third electrode indicated
18
, isolated from the frontal surface by a gate dielectric (not shown) which provides the gate terminal G of the transistor.
In the drawing there is also shown another n-type region, similar to the drain region
11
of the transistor M
2
, and indicated
11
′, isolated by a buried region
12
′ and a junction-isolation region
13
, able to contain another DMOS transistor or other components of the integrated circuit. The isolation regions
13
arid
13
′ of the two n-type regions
11
and
11
′ delimit a portion
19
of the substrate able to contain other components of the integrated circuit, not shown, for example the control circuits of a DMOS transistor bridge. In this portion of the substrate
10
there is only shown a region
20
strongly doped with p-type impurities which has a metal contact electrode
21
on its surface. This electrode, in the example shown, is intended to connect to a ground terminal, that is, a voltage reference terminal common to all the integrated circuit.
On the other major surface, or back, of the substrate
10
there is also provided a metal contact electrode
8
which is connected to ground. In general, the integrated circuit in the substrate
10
will have several r-type regions, such as the regions
11
and
11
′ isolated from the substrate by isolation regions such as the regions
13
and
13
′.
The body region
15
and the drain region
11
define between them a pn junction which provides the recovery diode Db
2
of the transistor M
2
in the bridge of FIG.
1
. Moreover, the body region
15
, the drain region
11
and the substrate
10
define, respectively, the emitter, base and collector regions of a bipolar pnp transistor, represented by its circuit symbol and indicated Qp
2
in FIG.
2
.
The transient situation described above, that is, where the source terminal of the transistor M
2
is at a higher potential than that of the supply Vcc arid the diode Db
2
is forward biased, is symbolized by a current generator
22
which injects a current, the recirculation current, into the source terminal S of the transistor M
2
. In this situation the base-emitter junction of the parasitic transistor Qp
2
is also forward-biased so that the transistor Qp
2
is conductive and a current is injected into the substrate. Because of the distributed resistance of the substrate, represented by two resistors Rsub
1
and Rsub
2
in FIG.
2
, this current causes a localized rise in potential within the substrate with respect to the ground potential. This can cause disturbances in the operation of the integrated circuit, in particular in the parts in which small signals are processed.
The ground contact formed by means of the region
20
and the electrode
21
provides a known approach for significantly reducing this effect. In practice the effect of the ground contact on the frontal surface is to divide the distributed resistance of the substrate, which is represented by a potential divider formed by two series resistors Rsub
1
and Rsub
2
, the intermediate tap of which is connected to the ground contact
20
,
21
.
The effects of the negative overvoltage on the drain terminal D of transistor M
1
are described in relation to FIG.
3
. The structure of the transistor M
1
is identical of that of the transistor M
2
of FIG.
2
and therefore the corresponding elements are indicated with the same reference numerals. In the drawing various n-type regions, indicated
11
″ have been shown, similar to the region
11
able to contain other DMOS transistors or different components of the integrated circuit, and a strongly doped p-type region
20
with an ground contact electrode
21
which has the function described above in relation to FIG.
2
. The drain region
11
of the transistor M
1
provides the emitter region of a parasitic bipolar npn transistor Qp
1
the base of which is distributed within the interior of the sub
Pedrazzini Giorgio
Pozzoni Massimo
Ravanelli Enrico Maria
Ricotti Giulio
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Chaudhari Chandra
Galanthay Theodore E.
STMicroelectronics S.r.l.
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