Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1999-10-28
2001-11-06
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S424000, C438S437000
Reexamination Certificate
active
06313011
ABSTRACT:
FIELD OF INVENTION
The present invention is generally directed to the manufacture of a semiconductor device. In particular, the present invention relates to a process of suppressing narrow width effects by controlling the Transient Enhanced Diffusion (TED) of the source/drain regions as well as boron segregation in a MOS transistor.
BACKGROUND OF INVENTION
The electronics industry continues to rely upon advances in semiconductor technology to realize higher-functioning devices in more compact areas. For many applications, realizing higher-functioning devices requires integrating a large number of electronic devices into a single silicon wafer. As the number of electronic devices per given area of the silicon wafer increases, the manufacturing process becomes more difficult.
A large variety of semiconductor devices has been manufactured having various applications in numerous disciplines. Such silicon-based semiconductor devices often include metal-oxide-semiconductor (MOS) transistors, such as P-channel MOS (PMOS), N-channel MOS (NMOS) and complementary MOS (CMOS) transistors, bipolar transistors, and BiCMOS transistors. Each of these semiconductor devices generally includes a semiconductor substrate on which a number of active devices are formed. The particular structure of a given active device can vary between device types. For example, in a MOS transistor, an active device generally includes a source and drain region and a gate electrode that modulates current between the source and drain regions.
One important step in the manufacturing of such devices is the formation of devices, or portions thereof, using photolithography and etching processes. In photolithography, a wafer substrate is coated with a light-sensitive material called photo-resist. Next, the wafer is exposed to light; the light striking the wafer is passed through a mask plate. This mask plate defines the desired features printed on the substrate. After exposure, the resist-coated wafer substrate is developed. The desired features as defined on the mask are retained on the photoresist-coated substrate while unexposed areas of resist are washed away. The wafer, with the desired defined features, is then etched. Depending upon the production process, the etching may either be a wet etch in which liquid chemicals are used to remove wafer material or a dry etch in which wafer material is subjected to a radio frequency (RF) induced plasma. A challenge in the etching process is maintaining control over the etching of the features, notably in the source/drain electrode regions of the MOS transistor. A further challenge is to control the electrical characteristics of the source/drain region by establishing a suitable doping profile that provides good conductivity within the constraints of design rules which trend further into the sub-micron range.
Doping the source/drain regions of a MOS transistor is typically accomplished through ion implantation. Unmasked areas of the MOS transistor are subjected to a beam of dopant atoms. Ion implantation has a number of advantages, including the ability to precisely control the number of implanted dopant atoms into substrates, for example, within ±3% in a range of about 1×10
14
to 1×10
18
atoms/cm
3
. A significant disadvantage to ion implantation is that it causes damage to the material structure of the target. In the single-crystal substrate of the source/drain region, crystal defects and some amorphous layers are formed. To restore the target material to its pre-implantation condition, thermal processing (e.g., annealing) after implantation must be performed. In some cases, significant implantation damage can not be removed. Damage at the source/drain region can lead to enhanced dopant diffusion or TED (Transient Enhanced Diffusion) of the doping species in the sub-micron realm where shallow source/drain regions are necessary. TED can contribute to the narrow width effect. In addition, the lateral distribution of implanted species (although smaller than lateral diffusion effects) is not zero. This is a limiting factor in fabricating some minimum sized device structures, such as the electrical channel length between source and drain in self-aligned MOS transistors.
In a prior art process, it has been observed that the threshold voltage (V
t
) increases as the transistor width (W) decreases from 2.0 &mgr;m to 0.4 &mgr;m. When shallow trench isolation is used, the V
t
difference may be greater than 100 mV and is undesirable. This behavior is not expected. This anomalous increase in V
t
with the decrease in W is similar to the TED effect described earlier as RSCE. Generally, the V
t
of a MOSFET decreases monotonically with decreasing channel length. In some situations, it has been found that V
t
initially increased with decreasing channel length (beginning when L~2-3 um), contrary to what is normally expected. The phenomenon observed is the RSCE (Reverse Short Channel Effect), a transient enhanced up-diffusion of the channel profile induced by source/drain implant damage.
The surface recombination of interstitials under the gate gives rise to impurity flux to the surface that raises the threshold voltage. Interstitials are atoms or ions of doping species that occupy spaces between the larger silicon atoms or ions in the crystal lattice. In a prior art process, NMOS devices can be fabricated with two boron channel implants. The first is a shallow boron implant for adjusting the threshold voltage; the second is a deeper implant for suppressing punchthrough.
The effect of the two-boron implant is noted on STI (shallow trench isolation) borders. Interstitials generated during S/D (source/drain) implant recombine at trench sidewalls, giving rise to an interstitial gradient and an impurity flux at the surface. The effect is more pronounced as W gets smaller and the implant damage in the trenches overlap on both sides. Consequently, dopant up-diffusion covers a larger percentage of the width.
In a PMOS transistor, the aforementioned effects do not occur. The P+ implant does not generate as much damage that tends to increase the threshold voltage. In an example process, the N+ implant after the LDD implant is omitted. The LDD implant serves as the source/drain of the transistor. The S/D damage and excess interstitials no longer are there. The V
t
versus W for devices without the S/D implant do not show the anomalous increase in V
t
. The lack of an anomalous increase in the V
t
supports the theory that implant damage and the subsequent TED result in the increase in V
t
as device width (W) is decreased. Furthermore, it has been observed that boron segregation to the trench sidewalls may lead to subsequent V
t
rolloff.
Accordingly, there is a need for a semiconductor device having a trench isolation structure that addresses the TED and boron segregation, is substantially free of defects, and does not add extra manufacturing costs as the process technology is approaching fractional microns in feature sizes.
SUMMARY OF INVENTION
The present invention is exemplified in a number of implementations, one of which is summarized below. According to one embodiment, a method for manufacturing a semiconductor device having shallow trench isolation comprises forming a trench region in a substrate having a having a depth and cross-section. In the trench region, the method forms a dielectric liner on the trench region.
Forming a dielectric liner according to the present invention, reduces the V
t
roll-up and V
t
roll-off effects that results in a flatter V
t
versus Width curve. Simulations have shown the effects are not only due to geometric STI corner effect and the resultant enhanced field but also to boron segregation to the trench sidewalls. A dielectric liner may consist of a nitrided oxide or silicon nitride that inhibits the boron segregation to the trench sidewalls.
In another embodiment, a method for manufacturing a semiconductor device having trench isolation comprises forming a trench region in a semiconductor substrate until a trench having a depth
Dang Trung
Koninklijke Philips Electronics N.V. (KPENV)
LandOfFree
Method for suppressing narrow width effects in CMOS technology does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for suppressing narrow width effects in CMOS technology, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for suppressing narrow width effects in CMOS technology will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2611857