Method for suppressing even order harmonics in a device that...

Electricity: measuring and testing – Impedance – admittance or other quantities representative of... – Calibration

Reexamination Certificate

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C324S623000

Reexamination Certificate

active

06909292

ABSTRACT:
A method for calibrating a low pass filter is disclosed. The low pass filter comprises a plurality of transconductor cells. The method comprises generating a test signal to the low pass filter and suppressing even-order harmonics due to transistor mismatches within the plurality of transconductor cells. By adding a small number of transistors, the mismatch-induced even order harmonics can be greatly reduced. Even-order harmonics are minimized through the application of a control voltage. A method for calibrating against transistor mismatch utilizing a CMOS transconductor that is based on the regulated cascode topology is disclosed. The method is designed to provide suppression of the even-order harmonics, a very small increase in power and a silicon area of the transconductor cell. A well-defined offset is provided by biasing one of the mismatched transistors.

REFERENCES:
patent: 4344029 (1982-08-01), Cabot et al.
patent: 6137370 (2000-10-01), Yamamoto
patent: 2001/0005151 (2001-06-01), Suematsu et al.
patent: 2002/0160740 (2002-10-01), Hatcher et al.

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