Method for substantially eliminating hold time violations in imp

Details Method for substantially eliminating hold time violations in imp Method for substantially eliminating hold time violations in imp

1991-08-20

1993-11-02

Kuntz, Curtis

Pulse or digital communications

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375106, 377 80, 307269, 371 1, H04L 706

Patent

active

052590062

ABSTRACT:
A method is provided for eliminating hold time violations in implementing high-speed logic circuits specified in circuit configuration data includes the steps of providing a synchronizer flip-flop device or latch corresponding to every flip-flop device or latch specified in the circuit configuration data. The synchronizer flip-flop is provided immediately upstream in the data path from its corresponding original user flip-flop device. A predetermined amount of delay is added to the user's original clock and data signals. A synchronizing clock signal generator provides a delayed synchronizer clock for each master clock in the circuit which is provided to each user flip flop.

REFERENCES:
patent: 4426713 (1984-01-01), Shimizu et al.
patent: 4698826 (1987-10-01), Denhey et al.
patent: 4755704 (1988-07-01), Flora et al.
patent: 4811364 (1989-03-01), Sager et al.
patent: 4949361 (1990-08-01), Jackson

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