Method for storing the control code of a processor allowing effe

Details Method for storing the control code of a processor allowing effe Method for storing the control code of a processor allowing effe

1986-09-16

1988-06-14

Fleming, Michael R.

Excavating

364200, 364900, 365200, G06F 900, G06F 700

Patent

active

047517034

ABSTRACT:
A method for storing the control code of a processor in a read only memory ROM (5) and in a read/write memory RAM (7) comprising a code area and a patch area. It consists in virtually dividing the control code in blocks of n instructions, storing the first instruction of each block into the code area of the read/write memory, and storing the n-1 following instructions of each block in the read only memory ROM. When an error is detected in at least one block, the first instruction of said block normally stored in the read/write RAM, is replaced by a branch instruction containing a branch address value so as to point to the patch area where the corrected block is stored.
This method is implemented using a specific addressing circuit.

REFERENCES:
patent: 3959783 (1976-05-01), Fressineau
patent: 4080648 (1978-03-01), Asano
patent: 4141068 (1979-02-01), Mager
patent: 4308590 (1981-12-01), Stettmaier
patent: 4334268 (1982-06-01), Boney
patent: 4542453 (1985-09-01), Patrick
Lehman, M., IBM Tech Disclosure Bulletin, "Variable Memory Structure", vol. 9, No. 9, Feb. 1967.

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