Computer graphics processing and selective visual display system – Computer graphics processing – Graphic manipulation
Reexamination Certificate
2002-10-23
2004-04-13
Bella, Matthew C. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphics processing
Graphic manipulation
C345S649000, C345S674000
Reexamination Certificate
active
06720978
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to memory management, and, more particularly, to a method for storing and retrieving data that conserves memory bandwidth.
Recent dramatic technological advancements in the fields of computers, semiconductors, and communications have led to a proliferation of products that are capable of real-time processing of digitized streams of multiple data types, such as audio, video, graphics, and communications data streams. Such products are commonly referred to as “multimedia products”. These multimedia products include multimedia personal computers (PCs), television set-top boxes, videoconferencing systems, High Definition Television (HDTV) sets, video telephony systems, Internet (Web) browsers, video arcade game systems, consumer video game consoles, and many others.
High-quality multimedia applications require enormous amounts of processing power, memory resources, and communications bandwidth, which requirements are continuously increasing due to the increasing variety and complexity of the multimedia data being processed. For example, many multimedia products must be capable of simultaneous, real-time processing of photorealistic 3-D graphics, CD-quality digital audio, full-motion digital video (e.g., MPEG-encoded video), and communications data streams. Until recently, each of these multimedia processing functions was handled by a separate, dedicated processor element. Typically, a separate, programmable Digital Signal Processor (DSP) is used to handle each multimedia data type, with each DSP functioning as a co-processor in conjunction with a host CPU. However, Philips Semiconductors' TriMedia Product Group has developed a new Very Long Instruction Word (VLIW) processor architecture for consumer multimedia applications that converges these different functions into a single multi-function processor, called the TriMedia processor. The TM-2000 processor, which is the latest version of the TriMedia processor, is a programmable DSP/CPU that combines a next-generation, programmable microprocessor core with a full set of innovative development tools to simultaneously process full-motion video (i.e., MPEG-2 digital video and DVD video), 3-D graphics, and CD-quality audio, and high-speed communications data streams. By combining these various functions on a single chip, which reduces cost, size and power demands, the TM-2000 processor makes possible the implementation of an advanced multimedia system at an affordable cost and with a smaller footprint. This implementation of multiple processing functions on a single chip is sometimes referred to as a “system-on-a-chip”.
With reference now to
FIG. 1
, there can be seen a high-level block diagram of the TM-2000 processor
20
. As can be readily seen, the TM-2000 processor
20
includes a VLIW CPU
22
supported by a dedicated on-chip data cache
23
and a separate, dedicated on-chip instruction cache
24
. The TM-2000 processor
20
also includes a plurality of on-chip, independent, DMA-driven multimedia I/O and coprocessing units
50
a
-
50
j
that will hereinafter referred to as “function units”. These on-chip function units
50
a
-
50
j
manage input, output, and formatting of video, audio, graphics, and communications datastreams and perform operations specific to key multimedia algorithms, thereby streamlining and accelerating the processing of these video, audio, graphics, and communications datastreams.
With continuing reference to
FIG. 1
, the TM-2000 processor
20
utilizes an external Synchronous Dynamic Random Access Memory (SDRAM)
30
(or, a Sychronous Graphics Random Access Memory (SGRAM)) that is shared by the function units
50
a
-
50
j
via a high-speed internal 32-bit bus
40
a
, and a 64-bit bus
40
b
. The 32-bit bus
40
a
connects to a main memory interface
41
through a bridge
43
. The 32-bit bus
40
a
and the 64-bit bus
40
b
will hereinafter be collectively referred to as the “data highway
40
”. Bus transactions use a block transfer protocol. The on-chip function units
50
a
-
50
j
can be masters or slaves on the data highway
40
. Programmable bandwidth allocation enables the data highway
40
to maintain real-time responsiveness in a variety of different applications.
Because the SDRAM
30
is a shared memory resource that is frequently accessed by the multiple function units
50
a
-
50
j
of the processor
20
via the data highway
40
, the two-way data traffic on the data highway
40
requires a large amount of memory bandwidth. Memory bandwidth is defined as the maximum rate (e.g., Mbytes/second) at which the data can be transferred between the SDRAM
30
and the function units
50
a
-
50
j
and the CPU
22
of the processor
20
. It is highly advantageous to minimize the amount or proportion of the overall memory bandwidth for the processor
20
that is consumed by any given one of the function units
50
a
-
50
j
and the CPU
22
within the processor
20
, in order to thereby improve the efficiency, speed, and overall performance of the processor
20
. In a worst case scenario, if the memory bandwidth is insufficient, bottlenecks can occur due to data traffic congestion on the data highway
40
, thereby resulting in improper operation of the system and/or system failure.
The processing of digital video datastreams is a function that consumes a large amount of the available memory bandwidth, due to the fact that this function requires extensive use of memory in order to execute the complex algorithms that are required to decode and process the digital video datastreams. For example, the decoding and processing of MPEG-2 encoded digital video datastreams requires many memory-intensive operations to be performed. In the context of the TM-2000 processor
20
depicted in
FIG. 1
, the function unit
50
a
, called “MPEG2 Coprocessor”, is responsible for decoding the MPEG-2 encoded digital video datastream received by the function unit
50
b
, called “Vin/TS-In2”, hereinafter referred to simply as “Video In”. The decoded digital video data is stored in the SDRAM
30
, and then the function unit
50
c
, called “HD-VO” (High Definition-Video Out), hereinafter referred to simply as “Video Out”, fetches the decoded digital video data, performs any required post-processing operations, and then outputs the decoded digital video data to a display device. One particularly memory-intensive operation that is required by the MPEG-2 decoding function is Motion Compensation (MC), due to the fact that it entails block-based processing on randomly distributed reference blocks of the digital video data stored in the SDRAM
30
, which demands frequent and random memory accesses.
Based on the above and other factors, and as will be appreciated by those skilled in the pertinent art, the function unit
50
a
(hereinafter referred to simply as the “MPEG-2 decoder”) consumes a considerable amount of the available memory bandwidth in the TM-2000 processor
20
. Thus, in designing future generations of this TriMedia processor family the amount of the memory bandwidth required by this function unit should be minimized. The present invention meets this design objective by providing a novel methodology for storing data in and fetching data from a memory. Moreover, as will become readily apparent to a person skilled in the pertinent art, the methodology of the present invention has utility in any device or system that could benefit therefrom, the TriMedia processor being discussed herein by way of example only. In general, the present invention has utility in any system that includes a memory that is accessed in a manner that requires a first memory bandwidth if the data is stored and retrieved in the conventional way, but only requires a second memory bandwidth that is less than the first memory bandwidth if the data is stored and retrieved in accordance with the methodology of the present invention.
SUMMARY OF THE INVENTION
The present invention encompasses, in one of its aspects, a method for storing a block of data consisting of N rows and M columns, which
Peng Sharon
Van Der Schaar Mihaela
Bella Matthew C.
Koninklijke Philips Electronics , N.V.
Monestime Mackly
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