Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2001-10-11
2003-11-11
Phung, Anh (Department: 2824)
Static information storage and retrieval
Floating gate
Multiple values
C365S185110
Reexamination Certificate
active
06646913
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention regards a method for storing and reading data in a multilevel nonvolatile memory.
2. Description of the Related Art
As is known, in a memory that uses, as elementary cell, a MOS transistor having a floating gate region that can be biased through a control gate region, the possibility is exploited of modulating the threshold voltage of the cell to distinguish two logic states: one state in which the floating gate region does not contain any charge, characteristic of an erased cell (logic “1”), and another state in which the floating gate region stores a number of electrons sufficient for determining a sensible increase in the threshold voltage, thus identifying a programmed cell state (logic “0”).
For reading the memory cell in a conventional two level memory, the control gate region is brought to a read voltage Vread, and the current flowing in the cell is read (
FIG. 1
a
): if the cell is written, its threshold voltage is higher than the read voltage, and hence no current flows; if the cell is erased, its threshold voltage is higher than the read voltage, and the cell conducts current.
The information contained in the memory cell is read via a read circuit or “sense amplifier” which compares the current of the cell with a reference current and outputs the datum stored in a digital form.
Multilevel nonvolatile memories have recently appeared on the market, i.e., memories in which more than one bit per cell is stored. In this type of memories, the charge stored in the floating gate region is further broken up to generate a number of distributions corresponding to 2
n
, where n is the number of bits that are to be stored in each cell. For example, in case of two bits per cell, the read circuit has to work with four threshold voltage distributions (
FIG. 1
b
), and no longer with two threshold voltage distributions (
FIG. 1
a
) as in the case of two level memories.
FIGS. 1
a
and
1
b
also show typical values of the threshold voltages.
Both in case of two level memories and in the case of multilevel memories, the distribution of the threshold voltages of the cells after electrical erasing is generally between about 1 V and 2.5 V. The lower limit of this distribution is given by the need to guarantee the absence of depleted cells (i.e., cells that conduct current even when a biasing voltage is not applied to their control gate region) and to prevent the thin oxide region beneath the floating gate region from being damaged during the write phase. The upper limit is instead due to the inherent amplitude of the distribution. In addition, the programmed level cannot be shifted above 6.5 V for reliability.
As may be clearly deduced from a comparison between
FIG. 1
a
and
FIG. 1
b
, multilevel programming entails a reduction in space between the distributions, and hence a reduction in the current differences that are to be detected in the read phase.
In particular, assuming a cell gain of 20 &mgr;A/V, in case of a two level memory there is a distance of 50 &mgr;A between the two distributions, whereas in case of a four level memory, there is a distance of 20 &mgr;A between the distributions, even though the higher distribution (corresponding to the bits “00”) has been set at a higher voltage compared to the case of the two level memory.
The reduction in the distance between the currents flowing in the cells for the different threshold voltage values requires designing read circuits that are increasingly complicated, more sensitive to noise, etc.
Reasoning on a binary scale, to increase further the number of bits to be stored in a single cell, it is necessary to store four bits per cell, corresponding to sixteen threshold voltage distributions in the same overall threshold voltage interval. Assuming a distribution amplitude of 200 mV and a distance between the different threshold voltage levels of 100 mV, we are faced with current differences of 2 &mgr;A.
In addition, as the integration density increases (at present, 0.13 &mgr;m technologies are used) the cell gain tends to decrease. Consequently, with a gain of 10 &mgr;A/V, the distance between the currents corresponding to two adjacent levels drops as far as 1 &mgr;A; i.e., it decreases by a factor of twenty compared to the case of two bits per cell. The accuracy required for passing from two bits per cell to four bits per cell is consequently far greater than that required for passing from one bit per cell to two bits per cell.
BRIEF SUMMARY OF THE INVENTION
An embodiment of the present invention provides a storing method allowing an increase in storing capacity of a nonvolatile memory without this weighing too heavily on the requisites of reading accuracy, complexity and criticality.
The method is for a multilevel non-volatile memory device composed of a memory array of a plurality of memory cells, and includes storing in each memory cell a number of bits that is not an integer power of two.
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patent: 5315558 (1994-05-01), Hag
patent: 5790454 (1998-08-01), Choi
patent: 5835414 (1998-11-01), Hung et al.
patent: 5854763 (1998-12-01), Gillingham et al.
patent: 5953255 (1999-09-01), Lee
patent: 6118692 (2000-09-01), Banks
patent: 6243290 (2001-06-01), Kurata et al.
patent: 6373767 (2002-04-01), Patti
Campardo Giovanni
Micheloni Rino
Iannucci Robert
Jorgenson Lisa K.
Phung Anh
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
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