Patent
1997-06-09
1999-07-27
Lall, Parshotam S.
395386, 395380, 395382, 395391, 39580023, 39580024, 395709, G06F 930, G06F 700
Patent
active
059305088
ABSTRACT:
A method and apparatus for compacting VLIW instructions in a processor having multiple functional units and including a buffer for storing compacted instructions, wherein NOP codes are eliminated from the compacted instruction and each compacted instruction includes words which contain an operation code directing the operation of one of the functional units, a dispersal code, and a delimiter code, wherein an alignment circuit parses each compacted instruction from the buffer based upon the delimiter codes of the words and aligns the compacted instruction in an alignment buffer and a dispersal circuit transfers each word of the compacted instruction stored in the alignment buffer into at least one operational field of a dispersed instruction buffer which stores an executable instruction having an operational field corresponding to each one of the functional units. Another embodiment is also shown which interleaves the bits of a buffer, alignment circuit, alignment buffer, dispersal circuit and dispersed instruction buffer to reduce the circuit area required for expanding the compacted instruction.
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Faraboschi Paolo
Raje Prasad
Hewlett--Packard Company
Lall Parshotam S.
Thomson William D.
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