Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1999-04-01
2001-05-01
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S431000, C438S433000
Reexamination Certificate
active
06225187
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to an STI process, and more particularly relates to an STI top-rounding process.
BACKGROUND OF THE INVENTION
With the increasing integration of ICs, hundreds of thousands of MOS transistors can be formed on a silicon substrate with an area of 1~2 cm
2
in an advanced VLSI process. In order to operate the transistors independently, each transistor must be isolated to prevent shorting. The process is called the “isolation process”.
A conventional isolation process comprises the following steps. First, an oxide and a hard mask are formed on a semiconductor substrate in sequence. Then, a window is defined at the determined STI site by using photolithography and etching techniques. Subsequently, the exposed substrate within the window is removed to form an STI trench. The detailed process is illustrated in FIGS.
1
A~
1
C.
First, referring to
FIG. 1A
, a semiconductor substrate
100
, such as a silicon substrate, is provided. Then, an oxide
110
(e.g. a silicon dioxide layer) and a hard mask layer
120
(e.g. a nitride layer) are formed on the semiconductor substrate
100
in sequence. Then, a photoresist pattern
130
with a opening
140
exposing the hard mask
120
at in a predetermined STI site is formed on the hard mask
120
by photolithography techniques.
Next, referring to
FIG. 1B
, the exposed hard mask
120
and the underlying oxide layer
110
and semiconductor substrate
100
within the opening
140
are etched to form an etching window
140
′ exposing the semiconductor substrate
100
by means of photolithography techniques.
Finally, referring to
FIG. 1C
, the photoresist layer
130
is removed, and the exposed semiconductor substrate
100
within the opening
140
′ is etched out by using the hard mask
120
as an etching mask, thus an STI trench
150
is formed. The STI trench
150
can be further gap-filled by an insulating material, though this step is not detailed here.
It is noted that the corners of the STI trench
150
are very sharp, therefore the STI channel obtained after gap-filling with an insulating material will make the insulating layer around the corners thinner than at other sites. Hence, leakage current or double hump may be apparent during operation, thus establishing a parasitic electric field.
In order to address the drawback of the conventional STI process described above, it is necessary to develop a novel STI process to forming top-rounded trenches for isolation.
SUMMARY OF THE INVENTION
In order to address the drawback of the conventional STI process described above, this invention discloses a method for STI top-rounding control.
The feature of the invention is to provide a method for STI top rounding control, the steps comprising: (a) providing a semiconductor substrate; (b) forming an oxide layer on the substrate; (c) forming a hard mask on the oxide layer; (d) forming a photoresist pattern with a opening exposing the hard mask at a predetermined STI trench region on the hard mask; (e) etching the exposed hard mask and the underlying oxide layer within the opening in sequence, and continuously over-etching to remove part of the semiconductor substrate to form a window lower than the surface of the oxide layer; and (f) using the photoresist pattern and the hard mask as etching masks, removing part of the exposed semiconductor substrate within the window to form an STI trench.
In the method described above, the semiconductor substrate is a silicon substrate. The oxide layer consists of a silicon dioxide layer. The hard mask can be nitride selected from the group consists of silicon nitride or silicon oxynitride. The etching process applied in step (e) is dry-etching, wherein the etchant is composed of a mixture of CHF
3
/CF
4
/O
2
/AR (Ar/CHF
3
ratio ranging from 3~6) or SF
6
/CHF
3
(ratio ranging from 1~3). The thickness of the removed substrate is about 100~300 Å. The etching process applied in step (f) is dry-etching, wherein the etchant is composed of a mixture of HBr/Cl
2
/O
2
(HBr/Cl
2
ratio ranging from 1~5). Moreover, the method described above can further comprise a step of gap-filling the STI trench with an insulating material to form an STI channel. The material used to gap-fill the STI trench can be, for example, silicon dioxide.
Other feature and advantages of the invention will be apparent from the following detailed description, and from the claims.
REFERENCES:
patent: 5258332 (1993-11-01), Horioka et al.
patent: 5578518 (1996-11-01), Koike et al.
patent: 5674775 (1997-10-01), Ho et al.
patent: 5968842 (1999-10-01), Hsiao
patent: 6005279 (1999-12-01), Luning
patent: 6153478 (2000-11-01), Lin et al.
Huang Tse Yao
Lai Yun Sen
Bednarek Michael D.
Dang Phuc T.
Nanya Technology Corporation
Nelms David
Pittman Shaw
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