Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2002-03-01
2004-08-10
Thai, Luan (Department: 2827)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C257S723000, C257S686000, C257S777000
Reexamination Certificate
active
06773959
ABSTRACT:
FIELD OF THE INVENTION
The invention pertains generally to stacking semiconductor package units to form a space-saving stacked package; and more particularly, to forming a stacked package without using a complex inter-unit structure.
BACKGROUND OF THE INVENTION
Many present electronic products comprise a number of semiconductor package units surface mounted on a printed circuit board (PCB) and connected together to form an overall circuit. A semiconductor package unit comprises an integrated circuit (IC) chip encased in a package comprising an insulating material (ceramic, plastic or the like) having a set of protruding leads. Bonding pads on the integrated circuit chip are electrically connected with bond wires to leads of the package. Other leads of the package may not be connected (NC) to the internal integrated circuit chip. External connections are made to the internal chip via the package's leads.
As electronic products continue to shrink in size, it is desirable to increase the number of components mounted on a unit area of PCB. One way to accomplish this is to provide a stacked semiconductor package that integrates semiconductor package units into a stacked unit having a footprint similar to one semiconductor package unit. Forming a stacked semiconductor package presents at least two problems: forming connections between leads of an upper semiconductor package and a lower semiconductor package; and retaining the ability to access, or select, each semiconductor package unit individually.
Some prior art methods such as that of Wakefield, et al. (U.S. Pat. No. 5,512,783) stack semiconductor package units having rotationally symmetrical lead layouts by placing a first semiconductor package unit upside-down on top of a second semiconductor package unit. Direct solder connections are then formed between selected leads of the upper and lower semiconductor package units. Understandably such an approach does not lend itself to stacking semiconductor package units in which each unit has the same orientation.
While such prior art techniques can avoid use of complicated intra-unit structures, the ability to select each semiconductor package unit independently is typically accomplished with an auxiliary inter-unit structure. In operation, a semiconductor package unit is accessed, or selected, by applying a signal to a chip-select (CS) lead. A semiconductor package unit may have more than one CS lead, each selecting a different functionality of the integrated circuit. When forming direct solder connections between leads of an upper semiconductor package unit and a lower semiconductor package unit, then, it is undesirable to form a direct solder connection between an upper CS lead and a lower CS lead. Doing so would mandate selecting a functionality of the upper unit simultaneously with a functionality of the lower unit. Typically, CS leads of the upper unit are shortened so as to not come in contact with the corresponding lead of the lower unit and the upper CS leads are connected to NC leads of a lower semiconductor package. Signals from external circuitry reaching the lower unit's NC lead will have no effect on the lower IC chip, but will select a functionality of the upper IC chip.
There are other leads for which it may be desirable to access each package's lead separately. One example is a clock enable (CKE) lead. Typically, digital IC chips contain a clock circuit that generates a periodic waveform utilized to time other calculations performed on the IC chip. It may be necessary, then, to enable the clocks of the semiconductor package units separately. Typically, this is accomplished as described for the CS leads above. Namely, CKE leads of the upper unit are shortened so as to not come in contact with the corresponding lead of the lower unit and the upper CKE leads are connected to NC leads of a lower semiconductor package.
In the case where the lead layouts of two semiconductor package units are identical, as shown in
FIG. 1A
, when the units are stacked, the CS and CKE leads of the upper unit are connected to NC leads of the upper unit, which can then be directly soldered to NC leads of the lower unit.
FIG. 1A
shows two semiconductor package units IC
A
and IC
B
. In this figure, leads
19
A
and
19
B
are CS leads and leads
15
A
and
15
B
are NC leads. The step of connecting CS lead
19
B
of the upper unit to NC lead
15
B
of the upper unit is conventionally accomplished by use of an auxiliary connector unit, such as shown in Kang (U.S. Pat. No. 6,242,285). An exemplary auxiliary unit may be a PCB board
80
B
with a wire placed to connect the leads, or, as shown in
FIG. 1B
, a piece of auxiliary material
90
placed between the plastic or ceramic package and the leads, containing a wire to connect the desired two leads. These auxiliary connector units add to the cost of the overall assembly. Further, such units can become unnecessarily complex and their use becomes more challenging as the distance between leads decreases.
Thus, there is a need for a stacked package of semiconductor package units having direct connections between leads of the upper and lower package units that requires no auxiliary connection unit between leads of the upper package.
The present invention provides such a package and a method for forming the package.
SUMMARY OF THE INVENTION
The present invention provides a stacked semiconductor package comprising at least an upper semiconductor package and a lower semiconductor package. Selected leads of the upper semiconductor package are preferably directly soldered to corresponding leads of the lower semiconductor package unit. Each semiconductor package unit can be independently selected, and each clock circuit in each semiconductor package unit can be independently enabled. A chip select (CS) lead of the upper semiconductor package unit is shortened, and a direct connection is provided between the shortened upper CS lead and a first upper not-connected (NC) lead, also on the upper semiconductor package unit. The first NC lead may then be directly connected to a lower NC lead directly beneath the upper NC lead. An analogous process is performed for a clock enable (CKE) lead of the upper semiconductor package unit. Advantageously the resultant structure does not require an auxiliary connector unit.
Other features and advantages of the invention will appear from the following description in which the preferred embodiments have been set forth in detail, in conjunction with the accompanying drawings.
REFERENCES:
patent: 6242285 (2001-06-01), Kang
Bachand Edward N.
Dorsey & Whitney LLP
Sampson Taiwan Ltd.
Thai Luan
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