Thermal measuring and testing – Thermal testing of a nonthermal quantity – Of susceptibility to thermally induced deteriouration – flaw,...
Reexamination Certificate
2000-01-19
2001-07-17
Metjahic, Safet (Department: 2858)
Thermal measuring and testing
Thermal testing of a nonthermal quantity
Of susceptibility to thermally induced deteriouration, flaw,...
C374S047000, C374S005000, C324S760020
Reexamination Certificate
active
06260998
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to thermal cycle/shock tests for evaluating the resistance of an electronic product to thermally induced stress and, more particularly, to a method for determining a thermal cycle/shock test profile having testing times for testing the resistance of an electronic product to thermally induced stress and for assessing the reliability of the electronic product under such stress.
BACKGROUND ART
The creep/fatigue of solder joints caused by the thermal expansion mismatch between components and a printed wiring board (PWB) is a major concern for electronic products under severe thermal environments. Currently, the reliability of the solder joints in electronic products is validated by thermal cycle/shock tests to a specified number of cycles. Product design engineers ask if a test specification is adequate to meet the reliability requirements. The task has been investigated using various methods and one of them is a simple closed-form solution to model solder creep/fatigue. However, these closed-form solutions are not sophisticated enough to accommodate the effect of time dependent creep behavior on thermal strain in solder joints.
Thermal fatigue crack initiation and propagation in solder joints is a potential failure mechanism that may induce durability problems in electronic products. For commonly used Pb/Sn eutectic solder the field operational temperatures could be as high as 75% of the alloy melting temperature. The operational temperature induces a significant amount of creep coupled with fatigue during temperature/power cycles. This is especially true for surface mount technology where the thermal-mechanical stresses/strains imposed on the solder joints are significantly larger than those in the plated-through-hole technology. It is believed that the low cycle fatigue life of solder joints is directly related to the maximum strain ranges or strain energy density in the solder joint. However, to account for the effects of temperature holding times, ramp rates, etc., the strain range and strain energy density used in the model should be determined from the stress-strain hysteresis loop during time dependent creep.
In general, the stress-strain hysteresis loop in a solder joint depends on (i) the difference in the coefficient of thermal expansion (CTE) between components and the PWB; (ii) temperature profiles including cycling range, ramp rate, and dwell time; (iii) size of the components and stiffness of the PWB; (iv) solder joint material properties (time and temperature dependent); and (v) solder joint geometry including type (such as leadless joint, gull-wing leaded joint, etc.), stand off height, fillet shape, inter metallic thickness, etc. All these factors also affect the maximum strain ranges that determine the life of the joints.
To calculate the time dependent strain range and strain energy density of solder joints, numerical simulation methods such as finite element analysis are used. These analysis techniques handle three types of solder joints: (i) leadless joints for chip capacitors, chip resistors, chip carriers, and flip chip bumps; (ii) leaded joints for gull-wing, J-leads, and butt leads; and (iii) interlayer joints for multi-layer stacks. The failure criteria for these joints can be developed and implemented for crack initiation life prediction.
The failure criterion for leadless joints is based on the total strain range determined by the temperature cycle profiles and solder elastic-viscoplastic properties. The approach to determine creep strain has been proposed through solving the following equations:
ⅆ
γ
ⅆ
t
+
1
k
ⅆ
τ
ⅆ
t
=
0
(
1
)
ⅆ
γ
CRP
ⅆ
t
=
B
τ
n
(
2
)
Δ
γ
+
Δ
τ
k
=
L
h
Δ
α
Δ
T
(
3
)
ⅆ
γ
ⅆ
t
-
ⅆ
γ
CRP
ⅆ
t
=
1
G
ⅆ
τ
ⅆ
t
+
τ
G
2
ⅆ
G
ⅆ
t
(
4
)
where L is the distance from solder joint to the middle of the component, h is the solder joint stand-off, &Dgr;&agr; is the CTE difference of the component and the PWB/substrate, &Dgr;T is the range of temperature cycles, &tgr; and &ggr; are the nominal shear stress and strain, G is the shear modulus, k is the stiffness constant depending on the materials and configurations of the component/substrate, and B and n are creep properties of the solder material.
For leaded components, the thermal stress range can be calculated by combining the shear and normal stresses. The leads are treated as simple beams, and solder joints are modeled as a temperature dependent elastic-plastic material. The time dependent effect is only considered through a frequency dependent parameter in the constitutive equation. The equivalent strain is determined in the joint along the lead foot length, and the local maximum value near the heel is used for fatigue life prediction.
For both cases, the fatigue life prediction is based on the Coffin-Manson relation:
N
i
=
C
[
Δ
γ
i
]
-
m
(
5
)
where the constants C and m are material dependent fatigue coefficients and N is the number of cycles to failure. In the field operation, the temperature applied to a solder joint is not within a constant range. Thus, if n
i
represents the stress cycles applied to a product, the fatigue life and the total cumulative damage D is estimated by Miner's rule as follows:
D
=
∑
n
i
N
i
=
∑
n
i
C
Δ
γ
m
(
6
)
Equation 6 is used to determine the fatigue life of solder joints based on the physics-of-failure approach and the estimation of the damage D.
In the automotive industry, product reliability is validated by a series of tests. Among them, accelerated thermal cycle/shock tests are used to check the integrity of solder joints and to validate product reliability. A typical test profile consists of one hour cycles with 15 to 25 minutes holding time at two temperature extremes. Thermal cycle/shock tests are conducted for a specified cycle duration (500 to 2000 cycles, i.e., 20 to 80 days).
A problem with typical thermal cycle/shock tests is that the number of cycles of the specified cycle duration does not correlate to the expected number of years of field operation for the product given a specified field temperature profile. Consequently, the number of cycles in the specified cycle duration is conservatively high resulting in wasted testing time and/or over designed products.
What is needed is a method for determining a thermal cycle/shock test profile tailored to an electronic product in which the resistance of the electronic product to thermally induced stress is to be tested. The advantage of having a test profile tailored to the electronic product to be tested is that the testing times of the test profile may be less than the specified cycle duration of typical thermal cycle/shock tests and the resulting profile represents the field operation environment more accurately than a generic specification.
DISCLOSURE OF INVENTION
Accordingly, it is an object of the present invention to provide a method for determining an accelerated thermal cycle/shock test profile having testing times for testing the resistance of an electronic product to thermally induced stress and for assessing the reliability of the product under such stress.
In accordance with the above object and other objects, the present invention provides a method for testing an electronic module to evaluate solder joint failures caused by thermally induced stress. The method includes determining a thermal shock endurance test profile that represents field temperature conditions. The time to failure of solder joints in the electronic module using numerical simulation techniques is then estimated. A design life duration for the electronic module is then selected. The design life duration of the electronic module is then compared with the estimated time to failure of the weakest solder joint, i.e., the solder joint with the estimated
Abrahamsson John Bengt
Frimenko Jacob
Garfinkel George Albert
Harris Robert Charles
Hu James M.
Metjahic Safet
Mollon Mark L.
Nguyen Vincent Q.
Visteon Global Technologies Inc.
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