Method for source/drain self-alignment in stacked CMOS

Details Method for source/drain self-alignment in stacked CMOS Method for source/drain self-alignment in stacked CMOS

1984-09-28

1986-08-05

Hearn, Brian E.

Metal working

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29576J, 29576W, 29578, 148 15, 148188, 148DIG164, 357 237, 357 42, 357 44, 357 59, H01L 2190, H01L 2176

Patent

active

046034684

ABSTRACT:
In stacked CMOS, a single gate in first level polycrystalline silicon is used to address both an N-channel device in the substrate and an overlaid p-channel device. The p-channel device has self-aligned source and drain regions formed by diffusing a dopant from doped regions underlying them. The doped regions are formed by planarizing a doped insulating layer, and etching the doped layer back to the upper level of the gate prior to deposition of a second polysilicon layer.

REFERENCES:
patent: 4272880 (1981-06-01), Pashley
patent: 4467518 (1984-08-01), Bansal et al.
patent: 4476475 (1984-10-01), Naem et al.
patent: 4488348 (1984-12-01), Jolly
patent: 4497108 (1985-02-01), Kurosawa
patent: 4502202 (1985-03-01), Malhi

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