Method for software pipelining of irregular conditional...

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Reexamination Certificate

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Reexamination Certificate

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06892380

ABSTRACT:
A method for software pipelining of irregular conditional control loops including pre-processing the loops so they can be safely software pipelined. The pre-processing step ensures that each original instruction in the loop body can be over-executed as many times as necessary. During the pre-processing stage, each instruction in the loop body is processing in turn (N4). If the instruction can be safely speculatively executed, it is left alone (N6). If it could be safely speculatively executed except that it modifies registers that are live out of the loop, then the instruction can be pre-processed using predication or register copying (N7, N8, N9). Otherwise, predication must be applied (N10). Predication is the process of guarding an instruction. When the guard condition is true, the instruction executes as though it were unguarded. When the guard condition is false, the instruction is nullified.

REFERENCES:
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patent: 6240509 (2001-05-01), Akkary
Bringmann Alex., “Enhancing Instruction Level Parallelism through compiler-controlled speculation”, Univ. of Illinois, 1995.*
Schlansker et al., “Achieving High Levels of Instructions-Level Parallelism with Reduced Hardware Complexity”, Nov. 1994, HPL-96-120, www.hpl.hp.com/techreports/96/HPL-96-120.pdf.*
Rau et al., “Code Generation Schema for Modulo Scheduled Loops”, ACM Proceedings of the 25th annual International Symposium on Microarchitecture, Dec. 1992, vol. 23, iss. 1-2.*
Rau et al., “Register Allocation for Software Pipelined Loops”, Jun. 1992, In Proc. of the ACM SIGPLAN'92 Conference on Programming Language Design and Implementation, pp. 283-299.

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