Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Slope control of leading or trailing edge of rectangular or...
Reexamination Certificate
2001-06-22
2003-02-04
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Slope control of leading or trailing edge of rectangular or...
C327S165000, C327S299000
Reexamination Certificate
active
06515527
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The invention relates generally to microelectronic circuitry. More specifically, the invention relates to a method of reducing noise due to current demand during clock transitions.
2. Background Art
In all microprocessor-based systems, including computers, the clock circuit is a critical component. The clock circuit generates a clock signal that is a steady stream of timing pulses that synchronize and control the timing of every operation of the system.
FIG. 1
shows a prior art diagram of an ideal clock signal
10
. An entire clock cycle
12
includes a rising or leading edge
14
and a falling or trailing edge
16
. These edges
14
,
16
define the transition between the low and high value of the signal.
Clock noise problems on the system power grid are usually caused by the large amount of current that is used in clock signal distribution. This current comes from the switching transistors that control the clock signal. As these transistors switch states, the current noise spikes onto the power grid due to the current demand or “current draw” of the switching transistors. These high current demands cause noise in the system voltage supply due to voltage (IR) drops and inherent system inductance (L di/dt). A clock signal distribution circuit uses a significant amount of current in a short amount of time because the spikes occur twice per clock cycle: once on the current draw of the leading edge and once on the current draw of the falling edge of the signal. This puts the noise at a very high frequency (
2
× the clock frequency). This noise can cause missed timing if the clock signal voltage is too low or component failure if the clock signal voltage is too high. The noise can even escape “off the chip” and affect the other components of the system.
FIG. 2
shows a prior art diagram of a clock distribution tree
20
. The initial clock signal (CLK
4
) is input into a series of load buffers
22
,
24
, and
26
. Finally, the clock signal (CLK
1
) is input into a large load buffer
28
which outputs the final clock signal (CLK
0
). Each of these buffers
22
,
24
,
26
, and
28
represents certain system components that place a load on the clock signal. The last buffer
28
represents the largest load of the system. Also, each buffer
22
,
24
,
26
, and
28
places a slight delay on the transmission of the clock to the next buffer. Consequently, the signal for each segment of the clock tree
20
CLK
4
, CLK
3
, CLK
2
, CLK
1
, and CLK
0
lags slightly behind the signal of the immediately preceding segment. In this embodiment of a clock tree
20
, the greatest current demand will come from the large load buffer
28
and it will consequently generate the greatest amount of noise.
FIG. 3
shows a prior art graph of a clock signal
30
. The signal is plotted as power (which is a function of current) versus time. As shown, the clock signal begins at the “LOW” value
32
and rapidly transitions
34
to the “HIGH” value
36
. After remaining at the “HIGH” value
36
for a specified period of time, the clock signal rapidly transitions
35
back to the “LOW” value
32
. Both transitions
34
and
35
take place in a very short period of time or “&Dgr;t”
38
. However, the circuit cannot effectively respond to the current demands in this short of a &Dgr;t. The demand is so great that the result is a significant amount of noise on the system, especially if the clock signal is serving a large load.
A common technique to alleviate noise is adding additional power to the grid. This power is added upon sensing a voltage drop due to noise. However, such techniques only respond to noise at a much lower frequency than clock noise and also respond only to a certain threshold of noise. Consequently, a need exists for a technique that generates a response to clock noise at a synchronized current draw.
SUMMARY OF INVENTION
In some aspects, the invention relates to a method for increasing a transition time period for an edge transition of a clock signal, comprising: detecting an edge transition of a clock signal; and initiating an additional system power consumption upon detecting the edge transition.
In another aspect, the invention relates to a method for increasing a transition time period for an edge transition of a clock signal, comprising: step of detecting an edge transition of a clock signal; and step of initiating an additional system power consumption upon detecting the edge transition.
In another aspect, the invention relates to an apparatus for increasing a transition time period for an edge transition of a clock signal, comprising: a control circuit that detects an edge transition of a clock signal; and a power consumption circuit that uses system power upon detection of the edge transition by the control circuit.
In another aspect, the invention relates to an apparatus for increasing a transition time period for an edge transition of a clock signal, comprising: means for detecting an edge transition of a clock signal; and means for using system power upon detection of the edge transition.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.
REFERENCES:
patent: 6069510 (2000-05-01), Keeth
patent: 6320438 (2001-11-01), Arcus
Amick Brian W.
liu Dean
Thorp Tyler J.
Cunningham Terry D.
Rosenthal & Osha L.L.P.
Sun Microsystems Inc.
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