Method for simultaneously forming an interconnection level and v

Details Method for simultaneously forming an interconnection level and v Method for simultaneously forming an interconnection level and v

1986-08-28

1988-01-26

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437198, 437228, 437245, 437 51, 20419211, C23F 102, C03C 1500, C03C 2506

Patent

active

047216891

ABSTRACT:
A method for simultaneously forming a level of interconnection metallurgy over, and inter-level via studs through, an insulating layer of a semiconductor chip. The method comprises the steps of forming a plurality of via holes in the insulating layer, high-mobility sputtering conductive material on to the surface of the insulating layer and into the via holes therein, masking the conductive material layer, and then ion beam milling through the mask to form a patterned interconnection layer. The high-mobility sputtering step is accomplished by reducing the background pressure to below 10.sup.-7 Torr to eliminate non-mobile species, maintaining a sputter pressure of less than 7 microns, maintaining an appropriate chip bias level to keep the conductive material molecules mobile until they reach their lowest energy state, and maintaining the temperature of the chip at a level so that a high sputter species mobility is maintained. This high-mobility sputtering forms a substantially planar conductive layer and fills the via holes without void formation. The foregoing process permits extremely dense interconnection levels, is especially suited for multiple interconnection level designs, and is extendable to large diameter wafer fabrication.

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