Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2001-09-12
2004-03-02
Nguyen, Matthew V. (Department: 2838)
Electricity: power supply or regulation systems
Output level responsive
Using a three or more terminal semiconductive device as the...
Reexamination Certificate
active
06700359
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to control of voltage regulators.
BACKGROUND OF THE INVENTION
The function of a voltage regulator is to provide a constant output voltage level even if the input voltage is poorly specified and fluctuating. Typically, the output of the voltage regulator is used as a supply voltage for other circuits in the system. As a consequence, the fluctuations and random variations in the supply voltage under changing load conditions are essentially eliminated.
Since the regulation and control of supply voltage is one of the most fundamental and critical requirements of the electronic system design, the monolithic voltage regulator or power control circuits have become some of the essential building blocks of any analog or digital system.
Today, there are two very distinctly different types of IC voltage regulators which have gained wide acceptance and popularity. These are series regulators and switching regulators. The series regulators control the output voltage by controlling the voltage drop across a power transistor which is connected in series with the load. The power transistor operates in its linear region and conducts current continuously. The switching regulator, on the other hand, controls the flow of power to a load by turning on and off one or more of the power switches connected in parallel or series with a load and make use primarily of inductive energy elements to convert the switch current pulses into a continuous and regulated load current.
In digital signal processor (DSP) systems, dual voltage power supply architectures are becoming more common place. Typically, to save power and to increase processing speeds, processing cores have smaller geometry cells and require lower supply voltages than system bus voltages. Consequently, power management in these types of systems is important.
In dual or multiple voltage architectures, coordinated management of power supplies is important to avoid potential problems and insure reliable performance. Timing and voltage differences must be considered between core and I/O voltage supplies during power up and power down operations. Sequencing the power supply refers to the order, timing and differential in which the two rail voltages are powered up and down. Ignoring proper sequencing may result in two types of failures. The first type of failure represents a threat to the long-term reliability of the dual voltage device. However, the second failure results in a more immediate threat with a possibility of damaging interface circuits in the processor or system devices such as memory, logic, or data converter ICs.
The long-term reliability of a dual voltage device maybe compromised from stress placed on internal circuits that connect portions of a chip powered by separate power rails. This type of stress is considered low level and occurs when one rail is active while the other rail is inactive. Typically, no permanent damage or reliability problems occur unless the condition persists over extended periods of time. However, cumulative exposure to uncontrolled power up and power down cycles can compromise the reliability of dual voltage devices in systems that are cycled on and off many times a day.
However, the reliability problem with interface circuitry can be immediate and catastrophic. Latch-up may occur when a processors, I/O interface and the I/O interface of a supporting peripheral such as memory, FPGA, or data converter are typically not powered from the same supply. Latch-up occurs when the current is forced through the substrate of a CMOS device and triggers a self-sustained conduction path in back to parasitic bipolar transistors. These parasitic transistors are unavoidable in most CMOS applications and form a structure similar to a SCR, connected between the power supply and ground. Once triggered, current continues to flow until the current is interrupted. The trigger current may occur if power is applied unevenly to the interfaces on the shared I/O bus. Yet another potential problem with improper supply sequencing is bus contention. Bus contention can occur when the processor and another device both attempt to control a bi-direction bus during power up.
To avoid these problems with the processor and system ICs, there are three general techniques for power up sequencing two or more power rails namely, sequential, ratiometric, or simultaneous. Sequential power up, as the name implies, powers up the two rails one after another. Typically, the second rail begins to ramp up once the first rail reaches regulation. Alternatively, the second rail may begin to ramp up after a set delay from the start of the first rail.
With the second or ratiometric method, the two rails begin to power up and reach regulation at the same time. This requires a higher slew rate for the rail with the higher final voltage, and results in the maximum voltage differential occurring when regulation is reached. However, some processors may not tolerate the instantaneous voltage differences that occur before regulation is reached, or the processor may draw high current from one supply during this period.
The third approach namely simultaneous eliminates instantaneous voltage differences and minimizes the magnitude and duration of stress. In this method, the voltage rails rise together and at the same rate with the higher or I/O voltage rail continuing after the lower or core voltage rail has reached its final value. One problem with simultaneous startup is the high current that results from the initialized logic within the DSP.
Thus, it is desirable to have a circuit to control two or more regulators to achieve simultaneous sequencing and satisfy the power requirements dual power logic devices.
SUMMARY OF THE INVENTION
The present invention controls two or more regulators by providing the feedback output of one regulator to control the output of the remaining regulators. Thus, an adaptive sample gain feedback scheme is achieved. The first regulator and second regulator start to increase the output voltage until the first regulator has reached a predetermined voltage. The second regulator's voltage does not continue to rise at the same rate. After the first regulator reaches the predetermined voltage, the second regulator is allowed to continue at a rate of rise that is determined by an R-C network.
REFERENCES:
patent: 4581690 (1986-04-01), Russell
patent: 5661643 (1997-08-01), Blakely et al.
patent: 6157550 (2000-12-01), Otake
patent: 6316970 (2001-11-01), Hebert
patent: 6342737 (2002-01-01), Brodeur
Daniels David G.
Fowler Tom
Brady W. James
Nguyen Matthew V.
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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