Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2000-07-20
2001-09-11
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S223000, C438S433000, C257S513000
Reexamination Certificate
active
06287937
ABSTRACT:
BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to the formation of semiconductor devices. More particularly, the present invention relates to the fabrication of locally doped regions within a semiconductive substrate. In particular, the present invention relates to a method of controlling well-drive diffusion by combining well drive with densification of an isolation film on a semiconductive substrate.
2. The Relevant Technology
In the microelectronics industry, a substrate refers to one or more semiconductor layers or structures which include active or operable portions of semiconductor devices. In the context of this document, the term “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term substrate refers to any supporting structure including but not limited to the semiconductive substrates described above.
In the microelectronics industry, the process of miniaturization entails shrinking the size of individual semiconductor devices and crowding more semiconductor devices into a given unit area. With miniaturization, problems of proper isolation between components arise.
When miniaturization demands the shrinking of individual devices, isolation structures must also be shrunk. Attempts to isolate components from each other are currently limited to photolithographic limits of about 0.2 microns for isolation structure widths.
To form an isolation trench, for example, by photolithography, the photoresist mask through which the isolation trench is etched generally utilizes a beam of light, such as ultraviolet (UV) light, to transfer a pattern through an imaging lens from a photolithographic template to a photoresist coating which has been applied to the structural layer being patterned. The pattern of the photolithographic template includes opaque and transparent regions with selected shapes that match corresponding openings and intact portions intended to be formed into the photoresist coating. The photolithographic template is conventionally designed by computer assisted drafting and is of a much larger size than a semiconductor substrate on which the photoresist coating is located. Light is shone through the photolithographic template and is focused on the photoresist coating in a manner that reduces the pattern of the photolithographic template to the size of the photolithographic coating and that develops the portions of the photoresist coating that are unmasked and are intended to remain. The undeveloped portions are thereafter easily removed.
The resolution with which a pattern can be transferred to the photoresist coating from the photolithographic template is currently limited in commercial applications to widths of about 0.2 microns or greater. In turn, the dimensions of the openings and intact regions of the photoresist mask, and consequently the dimensions of the shaped structures that are formed with the use of the photoresist mask, are correspondingly limited. Photolithographic resolution limits are thus a barrier to further miniaturization of integrated circuits. Accordingly, a need exists for an improved method of forming isolation trenches that have a size that is reduced from what can be formed with conventional photolithography.
The photolithography limit and accompanying problems of alignment and contamination are hindrances upon the ever-increasing pressure in the industry to miniaturize. Other problems that occur in isolation trench formation are, with trenches that are deep and wide in comparison to the size of the individual device that the trench is isolating, dielectric material such as thermal or deposited silicon oxide that fills the trench and tends to encroach upon the active area that the trench is designed to isolate. Another problem is that wide and deep trenches tend to put a detrimental amount of stress upon the silicon of the active area that leads to defects such as stress cracks, slip dislocations, and device failure.
Isolation trenches and active areas are often doped, either to enhance conductivity within an isolation area, such as an increased breakdown voltage at the bottom and/or in the walls of an isolation trench before filling the isolation trench with a dielectric material, or to increase the threshold voltage (V
T
).
For the fabrication of a complimentary metal oxide silicon (CMOS) device, ion implantation to form a preferred breakdown voltage and a preferred V
T
has been implemented by patterning a mask to first protect, for example, the N-well side of the CMOS device and then to ion implant the N-well portion of the device. Following ion implantation of the selected site, the photoresist material must be removed and the CMOS device must be patterned with a second photoresist material that is substantially opposite from the previous photoresist material. After patterning of the second photoresist material, the complimentary side of the semiconductor structure is ion implanted. This first mask/second mask technique was required to prevent contamination by the wrong type of dopant in each side of the CMOS device.
The first mask/second mask process involved several steps including the major steps of spinning on a photoresist material; curing; aligning a photomask template; exposing the photoresist material; removing developed portions of the photoresist material so as to form a pattern in the photoresist material; etching a desired topography through the patterned photoresist material, for example an isolation trench; ion implanting, for example the isolation trench and upon an active area; removing the patterned photoresist material; and then performing essentially the same steps over again for the semiconductor structure in a scheme that is substantially opposite to the first photoresist material.
Such an operation involves several possible chances for an erroneous fabrication step that will lower overall production yield. For example, where an isolation trench was formed by an anisotropic etch, a portion of the first mask is mobilized to begin to line the recess formed by the anisotropic etch. In such a case, stripping of the first photoresist material may require a stronger stripping solution than would other wise be needed. During photoresist material mobilization, the mobilized photoresist material may combine with other exposed portions of the semiconductor structure, such as metals, and thereby form a metal-polymer film within the recess being formed. Such a metal-polymer film resists stripping with conventional stripping solutions. A more effective stripping solution that removes a metal-polymer film, however, will likely also cause effacement of preferred topographies of the semiconductor structure that will compromise its integrity of the semiconductor structure.
It is preferable, at some point in fabrication of the isolation trench, to densify the fill material of the isolation trench. Densification is desirable because it helps to prevent separation of materials in contact with the fill material. It is sometimes preferable to perform densification of isolation trench fill material immediately following its deposition. Depending upon the specific application, however, densification may be carried out at other stages of the process. For example, densification of fill material by rapid thermal processing (RTP) may make either etchback or planarization of the semiconductor structure more difficult. As such, it has been preferable to density later in the fabrication process, such as after a planarizing or etchback processing.
It is also preferable at one point in the fabrication process, to thermally “drive in” an implanted well such as an N-well in a P-doped substrate. An example of a prior art well drive process includes formation of a P-doped region in a semiconductive substrate by
Gonzalez Fernando
Lee Roger
Blum David S
Chaudhari Chandra
Micro)n Technology, Inc.
Workman & Nydegger & Seeley
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