Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Computer or peripheral device
Reexamination Certificate
1998-07-22
2002-05-14
Frejd, Russell W. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Computer or peripheral device
C703S022000
Reexamination Certificate
active
06389382
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a simulator which can simulate a processor which executes pipeline processing of operation instructions, and a simulation method for a processor, using the simulator.
Recently, a processor in a multimedia market can execute real-time processing of video and audio of a dynamic scene as a result of improvement of operation performance. Further, a high-performance application can be formed by a personal computer, a portable terminal or the like.
However, when programming is performed by using a processor having such an operation performance, programming in a high-performance, complicated operation processing system is needed. Therefore, a simulator which can effectively debug a produced program is demanded.
2. Description of the Related Art
In the related art, a simulator does not exist which can simulate a processor which executes pipeline processing of operation instructions, executes operation processes in parallel in an order of inputting of the operation instructions (hereinafter, execution of the operation processes in the order of inputting of the operation instructions being referred to as ‘in-order execution’), and outputs results of the operation processes in an order of finish of the operation processes (hereinafter, outputting of the results of the operation processes in the order of finish of the operation processes being referred to as ‘out-of-order outputting’).
Further, when simulation of an ordinary processor, which performs pipeline processing of operation instructions, and performs in-order execution and in-order outputting, is executed, it is not necessary for a simulator in the related art to perform a simulation exact in the pipeline processing, but, in many cases, a sufficient simulation result can be obtained as a result of a simulation being performed in which single instructions are executed one by one. The above-mentioned ‘in-order outputting’ is outputting of results of the operation processes, the ‘in-order outputting’ being opposed to the ‘out-of-order outputting’. For example, the ‘in-order outputting’ is outputting of results of the operation processes in the order of inputting of the operation instructions.
On the other hand, as described above, a simulator does not exist which can simulate a processor which executes the pipeline processing of the operation instructions, and performs the in-order execution and out-of-order outputting. However, when a processor model described by hardware description language (HDL) is used, because this processor model is a rigid circuit, precise simulation of the processor can be executed.
However, although a simulator in the related art can perform a simulation of an ordinary processor which performs the in-order execution and in-order outputting, the simulator in the related art cannot execute processing in which execution of a certain operation instruction finishes before (passes) previously started execution of another operation instruction due to a differing number of execution cycles between the certain operation instruction and the other operation instruction executed in parallel therewith, with regard to simulation of a processor which performs in-order execution and out-of-order outputting.
Further, in the case where a processor model described by hardware description language (HDL) is used, precise simulation of the processor can be performed because the processor model is a rigid circuit as mentioned above. However, the simulation speed is low and a significant time is required for debugging of the program.
Further, in the case where a processor model described by hardware description language (HDL) is used, execution of an operation instruction may pass previously started execution of another operation instruction due to the number of execution cycles of each operation instruction which is executed in parallel with execution of the other operation instructions. As a result, the order in which results of the operation processes are obtained is not necessarily equal to the order described in the program. Therefore, it is difficult to detect errors in the program unless a description for detecting errors is added.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a simulator, in which execution of an operation instruction can pass previously started execution of another operation instruction due to in-order execution and out-of-order outputting, and a high-speed simulation and easy detection of errors in a program can be achieved as a result of detecting and indicating that execution of an operation instruction passes previously started execution of another operation instruction, a condition of waiting for enablement of an operation process occurring due to contention for a computing-unit resource, and an exceptional timing of outputting a result of an operation process occurring.
Another object of the present invention is to provide a simulation method using the above-described simulator.
A simulator, according to the present invention, can simulate a processor which performs pipeline processing of operation instructions, and performs operation processes in parallel, the number of the operation processes being larger than the number of the pipelines,
wherein the simulator simulates a passing operation in which a result of an operation process obtained from execution of the operation instruction is output earlier than a result of another operation process obtained from previously started execution of another operation instruction, the passing operation occurring due to the number of execution cycles of each operation instruction which is executed in parallel with execution of other operation instructions.
The simulator according to the present invention can perform simulation of not only an ordinary processor which performs in-order execution and in-order outputting, but also a processor which performs in-order execution and out-of-order outputting, and can simulate the passing operation.
Further, because the simulator according to the present invention does not perform simulation using a rigid circuit (simulation model), it is possible to achieve high-speed simulation and high-speed program. debugging, in comparison to the case where simulation is executed by using a processor model described with the hardware description language (HDL).
The simulator may comprises passing-operation detecting means (corresponding to a passing-operation detecting portion
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in an embodiment to be described later) for detecting occurrence of the passing operation.
In the simulator according to the present invention, similarly to the case where simulation is executed by using a processor model described with the hardware description language (HDL), the order in which results of the operation processes are obtained is not necessarily equal to the order described in the program due to occurrence of the passing operation. As a result of the passing-operation detecting means detecting occurrence of the passing operation, indication of the occurrence of the passing operation can be performed, and thereby, errors in the program can be easily detected.
The simulator may further comprises passing-operation searching means (corresponding to a passing-operation marking portion
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in the embodiment to be described later) for previously searching for an operation instruction, execution of which may cause the passing operation, before execution of the simulation,
wherein the passing-operation detecting means detects whether execution of the operation instruction, which has been found by the passing-operation searching means, actually passes previously started execution of another operation instruction.
Thus, the passing-operation detecting means detects whether execution of the operation instruction actually passes previously started execution of the operation instruction, only for the operation instructions which have been found by the passing-operation searching means. The passing-operation detecting means does not perfo
Kumamoto Norichika
Tanaka Ryuta
Frejd Russell W.
Fujitsu Limited
Staas & Halsey , LLP
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