Method for simulating cache operation

Details Method for simulating cache operation Method for simulating cache operation

1996-01-26

1998-12-01

Teska, Kevin J.

Boots, shoes, and leggings

364489, G06F 1203

Patent

active

058451064

ABSTRACT:
Multiple functional units of a computer system that typically access a secondary cache and the main memory system independently and simultaneously are simulated using RTL models which create such accesses using a random process. In one embodiment, an RTL model of each functional unit generates accesses to the cache memory according to a programmable frequency. The RTL models of these functional units also generate addresses which fall within programmable address limits and tag limits. In one embodiment, the functional units include data and instruction table lookaside buffers which traverse a two-level address translation scheme.

REFERENCES:
patent: 5392410 (1995-02-01), Liu
patent: 5442571 (1995-08-01), Sites
patent: 5493508 (1996-02-01), Dangelo et al.
patent: 5530833 (1996-06-01), Iyengar et al.
patent: 5530958 (1996-06-01), Agarwal et al.
patent: 5539907 (1996-07-01), Srivastava et al.

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