Excavating
Patent
1987-06-03
1989-09-19
Fleming, Michael R.
Excavating
364578, G06F 1520
Patent
active
048688258
ABSTRACT:
A method for simulating an open fault in a logic circuit comprising field effect transistors utilizes a simulation model which is employed and which takes the fault condition signal storage into consideration by way of an output stage. Given the appearance of a fault-influence signal at the output of a simulation stage, this maintains the through-connection of the signal which appeared immediately before the influenced signal to the simulation model output. In order to take reloading events in the real logic circuit into consideration, this through-connection is canceled after a prescribable time interval.
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Jain et al., "Test Generation . . . D. Algorithm", Proc. 20th Design Automation Conf., 1983, pp. 64-70.
Wadsack R. L. "Fault Modeling . . . Integrated Circuits", Bell System Technical Journal, vol. 57, No. 5, May-Jun. 1978, pp. 1449-1459.
Fleming Michael R.
Siemens Aktiengesellschaft
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