Boots – shoes – and leggings
Patent
1989-03-13
1992-10-20
Lall, Parshotam S.
Boots, shoes, and leggings
395500, G06F 1516
Patent
active
051576201
ABSTRACT:
A logic simulator has a time loop with a number of time slots into which events are scheduled. The events are wrapped around the loop, so that event times corresponding to different cycles around the loop may be simultaneously present on the loop. This allows a small loop size to be used, which improves performance. Preferably, the loop size is a prime number. If a complete cycle of the loop is made without finding any non-empty slots a jump is made to the next event time, so as to speed up the processing. In one described embodiment, the loop size is static, while in a second described embodiment the loop size is dynamically varied to minimize the insertion of events with different event times into the same slot.
REFERENCES:
patent: 4472789 (1984-09-01), Sibley
patent: 4677541 (1987-06-01), Singhi
patent: 4725971 (1988-02-01), Doshi et al.
patent: 4751637 (1988-06-01), Catlin
patent: 4901260 (1990-02-01), Lubachevsky
Abramovici et al.; "A Logic Simulation Machine"; IEEE Tran. CAD of Intog. Circuit and Syst.; Apr. 1983.
Howard et al.; "Parallel Processing Interactively Simulates Complex VSLI Logic"; Electronics Dec. 1983.
Van Norstrand; "Encyclopedia of Computer Science"; Litton Educational Publishing 1976.
Ulrich: Serial/Parallel Event Scheduling for the Simulation of Large Systems, Proceedings of the 1968 ACM National Conference pp. 279-287.
International Computers Limited
Lall Parshotam S.
Ramirez Ellis B.
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