Method for simulating a fault in a logic circuit and a simulatio

Details Method for simulating a fault in a logic circuit and a simulatio Method for simulating a fault in a logic circuit and a simulatio

1987-06-03

1989-07-25

Fleming, Michael R.

Excavating

364578, G06F 1520

Patent

active

048520934

ABSTRACT:
A method for simulating an erroneously-delayed signal switching at the output of the logic circuit utilizing a modified simulation model which is inherently suited for the simulation of a stuck-open fault and which, in particular, comprises an output stage which takes the signal storage appearing given this fault into consideration is disclosed. The modification is comprised in that the storage behavior of the output stage is suppressed after one clock period.

REFERENCES:
patent: 3715573 (1973-02-01), Vogelsberg
patent: 3780277 (1973-12-01), Armstrong
patent: 4156132 (1979-05-01), Hazzard
patent: 4228537 (1980-10-01), Henckels
patent: 4242751 (1980-12-01), Henckels
patent: 4308616 (1981-12-01), Timoc
patent: 4342093 (1982-07-01), Miyoshi
patent: 4669083 (1987-05-01), Laviron
Wadsack R. L., "Fault Modeling . . . Integrated Circuits", Bell System Technical Journal, vol. 57, No. 5, May-Jun. 1978, pp. 1449-1459.
Wadsack, "Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits".
Sunil Jain and Vishwani Agrawal, "Test Generation for MOS Circuits Using D-Algorithm".

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