Method for shrinking a clock cycle when testing high speed micro

Details Method for shrinking a clock cycle when testing high speed micro Method for shrinking a clock cycle when testing high speed micro

1996-06-27

1997-08-26

Nguyen, Hoa T.

Excavating

395556, G06F 104, G01R 3128

Patent

active

056617313

ABSTRACT:
A method for increasing the frequency of a particular clock cycle for a driven clock signal. The driven clock signal can be used to synchronize data transmission between circuit elements of a microprocessor. Accordingly, the particular clock cycle, with the increased frequency, will exercise a subset of the microprocessors circuit elements based on the instructions set being executed by the microprocessor. This timing method facilities speed path analysis for complex and high speed microprocessor designs.

REFERENCES:
patent: 5077686 (1991-12-01), Rubinstein

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