Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2003-03-21
2004-09-21
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S424000, C438S428000, C438S745000, C438S748000, C438S788000, C438S789000, C427S583000, C427S255280, C427S595000, C257SE21309, C257SE21582
Reexamination Certificate
active
06794270
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor integrated circuit fabrication, and in particular to the fabrication of void-free shallow trench isolation by spin spray etching.
2. Description of the Related Art
For semiconductor fabrication, active regions on a semiconductor substrate are defined by isolation structures, such as shallow trench isolation (STI) or recessed silicon dioxide isolation (ROI), used broadly in modern semiconductor fabrication. A conventional formation of a shallow trench isolation structure forms a trench on a predetermined region of a semiconductor substrate, filling the trench with insulating materials by chemical vapor deposition (CVD), and planarizing the surface of the semiconductor substrate by chemical mechanical polishing (CMP) to form shallow trench isolation with flat surface.
However, in highly developed IC design, the space between shallow trench isolation structures isolating active areas is narrowed to 0.11 &mgr;m or even less. Meanwhile, the aspect ratio (depth/width) of the shallow trench is above 3 or 4. Even if an HDPCVD with good filling capability is employed, voids or seams persist in the STI regions and one-step coverage is hard to achieve. When conductive materials are deposited in subsequent processes, these defects cause short circuits between devices, thus reducing the lifetime of the device.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a method of fabricating a high aspect ratio shallow trench isolation structure to prevent voids or seams in a STI structure thereby avoiding electrical defects.
To achieve the above-mentioned object, the present invention provides a method for shallow trench isolation fabrication. In an embodiment, a semiconductor substrate with a shallow trench thereon, i.e. with aspect ratio is 3 or above, is provided. An oxide layer is formed conformally on the trench and over the surface of the semiconductor substrate. The shallow trench is then filled with a liquid etching shield by spin-spraying. The uncovered oxide layer is subsequently removed by applying an etchant over the surface of the semiconductor substrate by spin-spraying, such that the oxide layer covered with the liquid etching shield is intact. To achieve the above process, the density of the etchant is less than that of the liquid etching shield.
In addition, after removing the upper portion of the oxide layer with the etchant, the etchant and the liquid etching shield are washed away with deionized water. Another oxide layer is then deposited on the oxide layer in the trench after the semiconductor substrate is thoroughly dried.
Accordingly, a shallow trench with thoroughly deposited isolation material can be formed without voids or seams in the trench on the semiconductor substrate, thereby improving the reliability of the semiconductor device.
Preferably, the spinning speed of filling the liquid etching shield is about 1000 to 1500 rpm and the spinning speed of spraying the etchant is between 1500 to 2000 rpm.
According to the present invention, the preferred liquid etching shield is a surfactant, such as polyacrylic acid or low cost chemical with high density, low viscosity and low toxicity, such as phosphoric acid, acetic acid or ethylene glycol.
According to the present invention, the preferred etchant is diluted hydrofluoric acid or buffered oxide etchant (BOE), for which the density is less than the liquid etching shield and insoluble with each other. More specifically, the density of the liquid etching shield at room temperature should be about 1.1 to 2.0 g/cm
3
with density of the etchant about 1 g/cm
3
.
In addition, the operating temperature is about 25 to 40° C., which can be achieved by elevating the temperature of the semiconductor substrate.
Preferably, the oxide layer is silicon oxide formed by high density plasma chemical vapor deposition (HDPCVD).
Preferably, the viscosity of the liquid etching shield should be lower than that of the etchant.
Moreover, the present invention further provides a method for removing partial oxide layer from a semiconductor substrate with a trench thereon, comprising subsequent steps. An oxide layer is formed on the trench and over the surface of the semiconductor substrate. The trench is filled with a liquid etching shield by spin-spraying. The upper portion of the oxide layer is etched subsequently by spin-spraying an etchant over the surface of the semiconductor substrate, such that the oxide layer covered with the liquid etching shield remains intact, wherein the density of the etchant is less than that of the liquid etching shield.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
REFERENCES:
patent: 5403630 (1995-04-01), Matsui et al.
patent: 5486234 (1996-01-01), Contolini et al.
patent: 5512767 (1996-04-01), Noble, Jr.
patent: 6455394 (2002-09-01), Iyer et al.
Chen Yi-Nan
Ho Tzu En
Lee Pei-Ing
Su Hsien Wen
Wu Chang Rong
Nanya Technology Corporation
Niebling John F.
Pompey Ron
Quintero Law Office
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