Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1997-04-28
1998-03-17
Dang, Trung
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438424, 438296, 438221, H01L 2176
Patent
active
057286213
ABSTRACT:
A new method for forming planarized high quality oxide shallow trench isolation is described. A nitride layer overlying a pad oxide layer is provided over the surface of a semiconductor substrate. A plurality of isolation trenches is etched through the nitride and pad oxide layers into the semiconductor substrate wherein there is at least one first wide nitride region between two of the isolation trenches and at least one second narrow nitride region between another two of the isolation trenches. A high density plasma (HDP) oxide layer is deposited over the nitride layer filling the isolation trenches wherein the HDP oxide deposits more thickly in the first region over the wide nitride layer and deposits more thinly in the second region over the narrow nitride layer and wherein the difference in step heights of the HDP oxide between the first region and a region overlying an isolation trench is a first height. A layer of spin-on-glass is coated over the HDP oxide layer wherein the difference in step heights of the spin-on-glass material between the first region and the region overlying an isolation trench is a second height smaller than the first height. The spin-on-glass layer and portions of the HDP oxide layer in the first region are etched away. The spin-on-glass layer and HDP oxide layer remaining are polished away wherein the substrate is planarized.
REFERENCES:
patent: 4842675 (1989-06-01), Chapman et al.
patent: 5182221 (1993-01-01), Sato
patent: 5242853 (1993-09-01), Sato et al.
patent: 5244827 (1993-09-01), Dixit et al.
patent: 5312512 (1994-05-01), Allman et al.
patent: 5494854 (1996-02-01), Jain
patent: 5498565 (1996-03-01), Gocho et al.
Chan Lap
Lu Wei
Tay Charlie Wee Song
Zheng Jia Zhen
Ackerman Stephen B.
Chartered Semiconductor Manufacturing PTE LTD
Dang Trung
Pike Rosemary L. S.
Saile George O.
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