Method for separation of diode array chips during fabrication th

Details Method for separation of diode array chips during fabrication th Method for separation of diode array chips during fabrication th

1989-11-21

1991-03-05

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437225, 437227, 437905, 357 17, 357 45, 156662, H01L 21302

Patent

active

049977920

ABSTRACT:
Rather than being separated along a single cleavage line between their adjacent ends, diode arrays are spaced apart on a fabrication wafer to allow parallel cleavage lines to be established between the ends of each adjacent pair of arrays by scribed grooves located along opposite sides of a narrow disposable strip of water material. A cleaving technique substantially insures that any projecting lip along the cleavage plane will be on the disposable strip rather than on a diode chip, so that such a defect cannot interfere with proper end-to-end spacing of the chips when they are subsequently assembled to provide a continuous row of chips with uniformly spaced individual light-emitting sites.

REFERENCES:
patent: 4068788 (1978-01-01), Gubitose et al.
patent: 4175684 (1979-11-01), Butler
patent: 4231503 (1980-11-01), Butler
patent: 4256246 (1981-03-01), Kindel
patent: 4355457 (1982-10-01), Barlett et al.
patent: 4604161 (1986-08-01), Araghi
patent: 4605944 (1986-08-01), Ishii et al.
patent: 4610079 (1986-09-01), Abe et al.
patent: 4668333 (1987-05-01), Tandon et al.
patent: 4814296 (1989-03-01), Jedlicka et al.
patent: 4822755 (1989-04-01), Hawkins et al.
patent: 4900283 (1990-02-01), Fukae
patent: 4904617 (1990-02-01), Muschke

Affiliated with

Also associated with

Rating

Method for separation of diode array chips during fabrication th does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for separation of diode array chips during fabrication th, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for separation of diode array chips during fabrication th will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-496570