Method for semiconductor device having radiation hardened...

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material

Reexamination Certificate

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C438S443000, C438S459000, C438S474000, C438S479000, C716S030000, C716S030000, C257S347000, C257SE21249, C257SE21563

Reexamination Certificate

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07943482

ABSTRACT:
A design structure is provided for a semiconductor device having radiation hardened buried insulators and isolation insulators in SOI technology. The device includes a first structure and a second structure. The first structure includes: a radiation hardened BOX layer under an active device layer; radiation hardened shallow trench isolation (STI) structures between active regions of the active device layer and above the radiation hardened BOX layer; metal interconnects in one or more interlevel dielectric layers above gates structures of the active regions. The second structure is bonded to the first structure. The second structure includes: a Si based substrate; a BOX layer on the substrate; a Si layer with active regions on the BOX; oxide filled STI structures between the active regions of the Si layer; and metal interconnects in one or more interlevel dielectric layers above gates structures. At least one metal interconnect is electrically connecting the first structure to the second structure.

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patent: 5589708 (1996-12-01), Kalnitsky
patent: 5795813 (1998-08-01), Hughes et al.
A. W. Topol, “Three-dimensional integrated circuits”; IBM j. Res. And Dev. vol. 50 No. 4/5; Jul./Sep. 2006.

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