Method for semiconductor chip packaging

Details Method for semiconductor chip packaging Method for semiconductor chip packaging

1998-05-28

1999-07-13

Picardat, Kevin M.

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Including adhesive bonding step

438106, 438116, H01L 2144, H01L 2148, H01L 2150

Patent

active

059239581

ABSTRACT:
A method for semiconductor chip packaging comprises the following processes: preparing an array-typed base plane by pressing a plane-shaped material, wherein said array-typed base plane comprises a plurality of single-united base surrounded and defined by latticed dams; mounting a already-cut die to each said base unit on said array-typed base plane, and adhering said die to said base unit; wire-bonding said mounted die; applying adhesive paste to top surface of each said dam, and covering the resultant structure with a transparent lid to ensure the hermeticity of the package; cutting said array-typed base plane to a plurality of single-united base. By above-mentioned process, the manufacturing cost can be reduced and the yield can also be enhanced.

REFERENCES:
patent: 5403783 (1995-04-01), Nakanishi et al.
patent: 5471027 (1995-11-01), Call et al.
patent: 5744863 (1998-04-01), Culnane et al.

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