Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2001-09-20
2003-09-16
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S113000, C438S460000, C438S976000
Reexamination Certificate
active
06620649
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and particularly to a method for manufacturing a semiconductor device using a flip chip type semiconductor chip (also called a “semiconductor element”).
This application is counterpart of Japanese Patent Applications, Serial Number 125368/2001, filed May 10, 2001, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
FIGS.
11
(
a
)-
11
(
d
) are diagrams for describing a conventional process for manufacturing or fabricating a semiconductor device. First of all, FIG.
11
(
a
) shows a semiconductor chip
1
corresponding to each of chips diced from a semiconductor wafer. An AL (aluminum) electrode pad is provided over the surface of the semiconductor chip
1
, and metal bumps
2
are formed over the pad. Next, as shown in FIG.
11
(
b
), the semiconductor chip
1
is flipped (turned upside down) to thereby bond the metal bumps
2
to a metal electrode placed over a mother board (circuit substrate)
3
by heating. Next, as shown in FIG.
11
(
c
), a liquid sealing or encapsulating resin
5
charged into a cylinder
4
drops onto one side of the semiconductor chip
1
. At this time, the encapsulating resin
5
is absorbed into a space or gap defined between the semiconductor chip
1
and the mother board
3
by a capillary phenomenon. The encapsulating resin
5
flows into the space toward the other side of the semiconductor chip
1
. As a result, the encapsulating resin
5
is charged into the space as shown in FIG.
11
(
d
). Thereafter, the encapsulating resin
5
is cured by heating. Thus, the space is sealed so that the semiconductor chip
1
and the mother board
3
are bonded to each other.
In the conventional process show in FIGS.
11
(
a
)-
11
(
d
), however, when a distance t
1
(see FIGS.
11
(
c
) and
12
(
a
)) provided between the semiconductor chip
1
and the mother board
3
is short, a shear frictional force (corresponding to a frictional force produced between the surface of the semiconductor chip
1
and that of the mother board
3
) of the encapsulating resin
5
surpass a sucking force developed by the semiconductor chip
1
and the mother board
3
and hence an uncharged portion
6
occurs. A problem arises in that when the unfilled portion
6
is formed, the surface of the semiconductor chip
1
cannot sufficiently be protected from an outer atmosphere. It is thus not possible to simply shorten the distance t
1
between the semiconductor chip
1
and the mother board
3
. As a result, it was difficult to reduce the thickness of the semiconductor device.
Each of Japanese Patent Application Laid-Open (Unexamined Patent Publications) Nos. Hei 11(1999)-340278, Hei 10(1998)-242208, Hei 9(1997)-97815, Hei 6(1994)-104311 and the like has disclosed the technology of firstly bonding an insulating or insulative adhesive film (insulative sealing or encapsulating resin sheet) onto the surface of a semiconductor chip when the semiconductor chip is placed over a mother board and next melting and curing the insulating adhesive film by heating.
Each of the above-described publications also describes the technology of firstly providing an insulating adhesive film within a gap defined between a semiconductor chip and a mother board when the semiconductor chip is placed over the mother board and next melting and curing the insulating adhesive film by heating. According to these technologies, the overall gap defined between the semiconductor chip and the mother board can be filled with an insulating resin.
In the conventional process using the insulating adhesive film, however, the insulating adhesive film is provided for each semiconductor chip. This means that the semiconductor device fabricating process gets longer in time. Further, the execution of a process step for providing the insulating adhesive film for each semiconductor chip or a process step for providing the insulating adhesive film between each semiconductor chip and the mother board means that the semiconductor device manufacturing process become long in time. As a result, the manufacturing cost of the semiconductor device increases.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method for fabricating a semiconductor device, which is capable of reducing production yields with a view toward solving the above-described conventional problems.
Another object of the present invention is to provide a method of fabricating a semiconductor device, which is capable of reducing a manufacturing process time. A further object of the present invention is to provide a method for manufacturing a semiconductor device, which is capable of reducing a manufacturing cost.
The present invention has been made to achieve the above objects. A typical method for fabricating a semiconductor device, according to the present invention is as follows: The present method includes a step for preparing a semiconductor wafer with a plurality of semiconductor elements formed thereon, a step for selectively providing insulating adhesives over respective predetermined areas of the semiconductor elements, and a step for fractionizing the respective semiconductor elements.
The above and further objects and novel features of the invention will more fully appear from the following detailed description, appended claims and the accompanying drawings.
REFERENCES:
patent: 5258325 (1993-11-01), Spitzer et al.
patent: 5776799 (1998-07-01), Song et al.
patent: 5824177 (1998-10-01), Yoshihara et al.
patent: 5863815 (1999-01-01), Egawa
patent: 5981360 (1999-11-01), Rabarot et al.
patent: 5994168 (1999-11-01), Egawa
patent: 6184109 (2001-02-01), Sasaki et al.
patent: 6319745 (2001-11-01), Bertin et al.
patent: 6322903 (2001-11-01), Siniaguine et al.
patent: 6344401 (2002-02-01), Lam
patent: 2002/0037631 (2002-03-01), Mimata
patent: 2002/0048906 (2002-04-01), Sakai et al.
patent: 06104311 (1994-04-01), None
patent: 09097815 (1997-04-01), None
patent: 09252025 (1997-09-01), None
patent: 11340278 (1999-12-01), None
Niebling John F.
Oki Electric Industry Co. Ltd.
Roman Angel
Volentine & Francos, PLLC
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