Method for selective filtering

Details Method for selective filtering Method for selective filtering

2001-01-02

2002-08-20

Malzahn, David H. (Department: 2121)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S319000

Reexamination Certificate

active

06438567

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for selective filtering with a coefficient and filter calculation unit, a phase detector, a loop filter, and a digital oscillator, these units simulating different selective filters depending on coefficients used for the filter calculation.
Systems for receiving digital data generally require a device for recovering the data clock signal implicitly contained in the signal. In principle, there are two approaches for receiving the data: (1) the clock control loop contains the circuit that supplies the sampling clock of the analog/digital converter (“ADC”) (e.g. VCXO); and (2) the clock signal of the ADC is asynchronous with respect to the data clock. A fully digital control circuit calculates by interpolation from the output values of the ADC samples in a timing pattern that is synchronous with the data clock. There exist prior art circuits that achieve the task in baseband. Most applications have filters upstream or downstream of the ADC, which filters select the signal that is intended to be processed, i.e., suppress adjacent signals and other interference signals. These filters are generally optimized for a fixed bandwidth or data rate, such as, e.g., surface acoustic wave filters. Stringent requirements regarding phase linearity are usually imposed on the filter so that the pulse shape of the data signals is not distorted.
Basic theories with regard to fully digital clock recovery in digital modems by interpolation are discussed in an article by Floyd M. Gardener titled “Interpolation in Digital-Modems -Part I: Fundamentals”. The article appeared in the journal IEEE Transactions on Communications, Vol. 41, No. 3, in March 1993.
A further approach in the prior art uses analog filters having a controllable bandwidth upstream of the ADC. However, these filters are expensive and, particularly in CMOS technology, are difficult to integrate on a circuit. Analog filters fundamentally have phase distortions that have to be reduced using additional circuits. Moreover, the sampling frequency of the ADC has to be adapted to the signal bandwidth.
Another approach lies in providing a multistage digital selection filter upstream of the clock recovery and in carrying out the fine adjustment of the sampling frequency by interpolation again. After each stage of the filter, the sampling rate is reduced by a fixed factor. The approach has a disadvantage in that many filter stages are required for small bandwidths. Thus, the filter becomes complicated. Moreover, a fixed gradation means that not all the interference components can be suppressed, which generally leads to an increase in outlay in the downstream interpolator.
Lambrette U et al.: “VARIABLE SAMPLE RATE DIGITAL FEEDBACK AND TIMING SYNCHRONIZATION” in I.E.E.E. Vehicular Technology Conference, New York, USA, I.E.E.E., Bd. Conf. 47, pages 1348-1352, discusses two algorithms for digital receivers for processing a broader range of different sampling rates. One of the algorithms is also based on filtering the received signals prior to the time synchronization. A time synchronization algorithm is presented that is not data-aided, is based on digital feedback, and can process symbol rates deviating from a sampling rate.
The paper by D. Kim et al.: “DESIGN OF OPTIMAL INTERPOLATION FILTER FOR SYMBOL TIMING RECOVERY” in I.E.E.E. Transactions on Communications, I.E.E.E. Inc., New York, USA, Vol. 45, No. 7, pages 877-884, discloses an optimized interpolation filter for recovering the symbol timing in a digital receiver, in which the sampling rate of the analog-to-digital converter on the input side is not synchronized with the symbol clock of the transmitter.
The paper by K. Bucket et al. “PERIODIC TIMING ERROR COMPONENTS IN FEEDBACK SYNCHRONIZERS OPERATING ON NONSYNCHRONIZED SIGNAL SAMPLES” I.E.E.E. Transactions on Communications, I.E.E.E. Inc., New York, USA, Vol. 46, No. 6, pages 747-749, reveals that the synchronization error contains periodic components through a loop for timing recovery on detection of nonsynchronized samples of a noisy sine signal. These periodic errors are produced exclusively by non-ideal interpolation between the nonsynchronized signal samples and disappear when synchronized sampling is performed.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for selective filtering that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that can be realized with little outlay.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a method for selective filtering, including the steps of simulating different selective filters with a coefficient and filter calculation unit, a phase detector, a loop filter, and a digital oscillator depending on first and second coefficients used for filter calculation, determining the first coefficients of a prototype of a further selective filter at a characteristic frequency fc for—given sampling frequency fa, calculating the second coefficients of the further selective filter at a characteristic frequency fc2 from the first coefficients at points t
k
=&Dgr;t+k*d, where k=0, 1, . . . , the further selective filter to be operated at a sampling rate fa
1
, by interpolating values of a continuous-time impulse response of a simulation of the further selective filter at points t
k
, where
d
=
fc2
*
fa
fc
*
fa
1
,
simulating the further selective filter with the second coefficients using the coefficient and filter calculation unit, the phase detector, the loop filter, and the digital oscillator, and operating the further selective filter at the sampling rate fa
1
.
The approach employed by the invention is to use a filter disclosed in International PCT publication WO-A-00/02311, filed Jan. 13, 2000, corresponding to PCT/DE 99/01878 and U.S. patent application Ser. No. 09/752,923 filed Jan. 2, 2001 by the same inventor and to combine it with a variant of a prior art clock recovery circuit with an interpolation filter. As such, the approach of deriving filter coefficients from the coefficients of a prototype filter is extended in order to additionally realize a variable delay that is required for the interpolation of the data signal and that must generally be shorter than the period of the ADC clock signal. Moreover, use is made of the fact that the filter bandwidth is always proportional to the data rate, i.e., the bandwidth and the decimation factor of the filter are in a fixed relationship with respect to one another. Correspondingly, in qualitative terms, there is more time available for calculating an output value of the filter, the lower the data rate or the bandwidth of the filter. On the other hand, it is also the case that more coefficients are required for calculating the output value given a smaller bandwidth. Meaning, in quantitative terms, that the same number of arithmetic operations per second is always required regardless of the data rate or the filter bandwidth. A suitable circuit is described below. A variant that is optimized in respect of outlay is likewise presented, for a case where the operating clock of the circuit is higher than the sampling clock at the filter input.
The circuits described below accomplish two tasks: (1) to realize low-pass filters having a bandwidth proportional to the data rate for suppressing adjacent signals; and (2) generating an output signal that is phase-synchronous with the data clock by interpolation because the sampling clock of the input signal is not synchronous with the data clock (free-running oscillator).
In order to accomplish the second task, a control loop including a phase detector, a loop filter, and a digital oscillator (“DTO”) is used. The oscillator is realized as an overflowing accumulator. If an overflow occurs, then a sample is interpolated from the samples of the input signal and feeds the phase detector and downstream circuits. In the steady-state condition, some of these interpolated

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