Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Patent
1998-08-25
2000-07-25
Teska, Kevin J.
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
703 19, 714 25, 714726, 714741, G06F 1750
Patent
active
060932120
ABSTRACT:
Operation cycles to be subjected to an IDDQ test are selected from among operation cycles defined by a test pattern for a functional test of a CMOS integrated circuit so that a sufficient and necessary number of operation cycles are accurately and rapidly selected. A combination of sets of m-bit data are selected so that the combination includes sets of m-bit data each bit of which is changed from one of the values "0" and "1" to the other at least once. The operation cycles corresponding to the sets of m-bit data included in the combination are rendered to be the IDDQ test cycles to be subjected to the IDDQ test.
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Takahashi Toshihiro
Tsukamoto Yasutaka
Choi Kyle J.
Ricoh & Company, Ltd.
Teska Kevin J.
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