Semiconductor device manufacturing: process – Semiconductor substrate dicing
Reexamination Certificate
2001-06-25
2002-06-18
Niebling, John F. (Department: 2827)
Semiconductor device manufacturing: process
Semiconductor substrate dicing
C438S465000
Reexamination Certificate
active
06406979
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for sectioning a substrate wafer into a plurality of substrate chips
BACKGROUND INFORMATION
Microelectronic components, such as computer chips or electronics chips, are typically produced within the framework of so-called planar technology. In this context, the substrate wafers made of a material suitable as a carrier material for the component, such as silicon, are coated in a series of subsequent coating and patterning steps with a suitable sequence of layers of the respective material later active in the component. In this context, after coating with a material, this material layer patterned, e.g., using patterning methods based on photoresist. The patterning ensures that the final material layer only covers those parts of the component-chip surface that require coating by the particular material for functional reasons.
Especially in the field of the mass production of components, a plurality of components is typically produced in parallel in one operation, in a particularly timesaving and cost-effective manner of manufacture. In this context, a comparatively large substrate wafer having a diameter of about 6 or 8 inches, for example, is coated according to the described method, a plurality of components being ultimately disposed next to one another on the surface of the substrate wafer. In other words, the multi-layered patterns necessary for a plurality of components are simultaneously produced by coating the substrate wafer.
Subsequent to the coating and patterning process, the components are present on one single substrate wafer. Therefore, an additional step is necessary in which the substrate wafer is sectioned into a plurality of substrate chips in such a manner that, in each case, every substrate chip only carries the layer structure intended for an individual component.
For this purpose, the substrate wafer typically undergoes a saw process after coating and patterning are completed. In this process, the substrate wafer is cut by a diamond-covered saw blade first in a line-by-line manner and then in a column-by-column manner. For this purpose, the substrate wafer is laminated or mounted onto a carrier film. Rotating the typically ring-shaped saw blade at a frequency of up to 20,000 rpm results in an abrasive material removal along the so-called saw cut.
However, due to the necessary material removal in a horizontal as well as vertical direction, such a saw process requires at least two process steps and is, therefore, time-consuming. In addition, the saw process essentially permits only a rectangular surface area for the substrate chip produced by sectioning; due to the increased number of necessary cutting directions, a comparatively more complicated surface area, e.g., in the shape of a polygon, would result in an even more unfavorable expenditure of processing time. Thus, with respect to the attainable surface areas of the substrate chip, the saw process has only limited flexibility.
SUMMARY
An object of the present invention is to provide a method for sectioning a substrate wafer into a plurality of substrate chips, the method enabling a process management that is especially timesaving and flexible with respect to the producible substrate-chip surface areas.
With regard to the method, this objective is achieved according to the present invention in that the substrate chips are separated from one another by a selective deep patterning method.
In this context, a deep patterning method is a method in which a laterally bounded material removal can be adjusted in a targeted manner, there being a preferential direction of the material removal into the depth of the processed material. In a selective deep patterning method, the removal action is additionally limited to a defined group of target materials.
The present invention is based on the consideration that the particular time expenditure resulting from the typically provided saw process, on the one hand, and the limited flexibility, on the other hand, are dependent on the driving direction of this process, namely in a lateral direction or in a direction parallel to the surface of the substrate wafer. However, the substrate wafer can be sectioned in a manner that is timesaving as well as flexible with respect to the achievable surface areas for the substrate chips in that a process is provided for segmenting that has a driving direction leading into the substrate wafer and oriented in a direction perpendicular to its surface. This can be achieved by a deep patterning method having a preferential direction into the substrate wafer due to the physical-chemical marginal conditions.
For a particularly extensive possible scope of application, a silicon wafer is advantageously sectioned as the substrate wafer, a selective deep patterning method for silicon being used. In this context, a material having a particularly effective removal action especially for silicon due to its physical-chemical properties is used as the patterning agent or etchant.
In one embodiment, a plasma etching method is used as the deep patterning method. In such a plasma etching method, the substrate wafer to be sectioned is exposed to an atmosphere of a etching gas. By supplying energy into the etching gas, e.g., using microwave irradiation, the gas is partially ionized and, therefore, forms a plasma. A portion of the thereby produced plasma ions, e.g., the positively charged cations, are then accelerated by an accelerating voltage toward the substrate wafer and impinge in an almost vertical direction upon the wafer's surface. In response to the impingement, the ions accelerated in the plasma react with the material of the substrate wafer, volatile reaction products being produced, and the material of the substrate wafer being locally dissolved. Furthermore, the accelerated ions knock off debris from the surface of the substrate wafer, thereby employing an etching operation. In response to the surface areas of the substrate wafer that are not to be etched being suitably covered, this process can be restricted to the desired separation areas.
As a result of the impingement direction of the ions upon the surface of the substrate wafer, such a plasma etching process exhibits a characteristic preferential direction of the removal process into the depth of the substrate wafer and is, therefore, particularly suitable as a deep patterning method. In addition, all of the surface areas of the substrate wafer can be parallelly and simultaneously processed, without the etching action being affected, e.g., by the crystal directions of the substrate wafer. Thus, the most different substrate-chip surface areas can be produced in a particularly simple manner. When processing a substrate wafer made of silicon, an SF
6
plasma may be used as the etching plasma. In an additional or alternatively advantageous embodiment, the etching plasma includes xenon difluoride (X
e
F
2
) or chlorine trifluoride (Cl F
3
).
In a particularly advantageous further refinement, an etching step and a polymerization step, respectively, are carried out in an alternating sequence in the plasma etching method. In this context, the etching steps and polymerization steps are controlled independently of one another. In this context, a polymer is applied during every polymerization step, in a lateral region predefined by an etching mask, the polymer being removed again during the subsequent etching step. The sequence of separate etching steps and polymerization steps ensures, on the one hand, a particularly high degree of anisotropic etching with high selectivity, a simultaneous presence of etchants and polymer formers in the plasma being reliably prevented, on the other hand. Thus, a particularly high etch rate can be achieved, almost neutral etching edges being able to be produced in the substrate wafer.
For a particularly high level of variability in the sectioning method with respect to predefined process parameters, such as a maximum allowable processing time, the plasma pressure, the plasma power, and/or acceleratio
Fischer Frank
Graf Eckhard
Kenyon & Kenyon
Zarneke David
LandOfFree
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