Electrical computers and digital processing systems: processing – Instruction issuing
Patent
1996-08-20
2000-04-11
Maung, Zarni
Electrical computers and digital processing systems: processing
Instruction issuing
712215, 712216, 712221, 712223, 712 23, 712 32, 712 41, 712245, G06F 940, G06F 938
Patent
active
060498641
ABSTRACT:
A method for scheduling a flag generating instruction and a subsequent instruction. The subsequent instruction has a data dependency on the flag generating instruction. The flag generating instruction is translated into first and second instructions. The subsequent instruction is translated into at least a third instruction. The first instruction, when executed, generates a result and intermediate flag generation data. The second instruction, when executed, generates a plurality of flags. The first instruction is scheduled to execute before the second and third instructions. The second instruction is scheduled to execute before the third instruction if the third instruction has a data dependency on the second instruction, otherwise the third instruction may be scheduled to execute before the second instruction.
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Hammond Gary
Liu Kin-Yip
Pai Anand
Shoemaker Ken
Yellamilli Krishna
Barot Bharat
Intel Corporation
Maung Zarni
LandOfFree
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