Method for scalable architectures in stackable...

Details Method for scalable architectures in stackable... Method for scalable architectures in stackable...

2006-05-16

2006-05-16

Vigushin, John B. (Department: 2841)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C257S686000, C257S698000, C257S724000, C257S777000, C438S109000, C174S262000

Reexamination Certificate

active

07046522

ABSTRACT:
The design methods described enable three-dimensional integrated circuit systems in which all of the dies, in a vertically bonded stack of dies, are identical. Only one mask set and wafer type is required since a single circuit design is produced for one die in the stack and reused for all the dies with little or no modification. The system scales directly as the level of stacking is increased while incurring no extra design effort, beyond that required for the initial design.

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Definition of “wafer” on the Web (GOOGLE): en.wikipedia.org/wiki/wafer—(electronics).

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