Gas: heating and illuminating
Reexamination Certificate
1999-01-25
2001-09-18
Utech, Benjamin L. (Department: 1765)
Gas: heating and illuminating
69, 69, 69, 69, 69
Reexamination Certificate
active
06290631
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming an integrated circuit device. More particularly, the present invention relates to a method capable of restoring the alignment mark on a substrate to the top of a dielectric layer after planarization.
2. Description of Related Art
Photolithography is a critical process in the fabrication of semiconductor devices. Depending on the complexity of the semiconductor device, the number of photoresist depositions and light exposure operations from 10 to 18. Hence, in order to transfer correctly a pattern to a wafer, the photomask must be properly aligned before the photoresist is exposed to light.
In conventional photo-exposure operation, alignment marks must be formed on the silicon wafer so that the alignment marks are able to match with the corresponding marks on the photomask. Step height of an alignment mark is capable of providing a scattering field or a diffraction edge. When a laser light source, for example, a helium-neon (He—Ne) laser having a wavelength of 635 nm shines on the alignment mark, a diffraction pattern is generated. The diffraction pattern can be reflected back and intercepted by an alignment sensor or a first order diffraction interferometer alignment system for recording the positional data. However, if the step height of the alignment mark of the wafer is below a threshold of 200Å, for example, the amount of diffraction generated by the alignment mark is too small to produce a strong alignment signal. In other words, when the noise ratio is too big, return signal from the alignment mark is too weak for the alignment sensor to determine the correct position.
FIGS. 1A through 1C
are cross-sectional views showing the steps according to a conventional method of fabricating a semiconductor device. First, as shown in
FIG. 1A
, a local oxidation of silicon (LOCOS) method or a shallow trench isolation (STI) method is used to provide an isolation region
102
on a substrate
100
. Thereafter, an alignment mark
106
is formed by etching the substrate
100
to form a trench
104
. The step height
170
or the difference in height level between the upper surface
160
of the substrate
100
and the bottom
150
of the trench
104
is roughly 1000Å. Next, a gate terminal
108
and two source/drain regions
110
are formed in sequence within the active device area bounded by the isolation structure
102
. Hence, a field effect transistor
112
is formed. Then, a dielectric layer
114
is formed over the substrate
100
for isolating the field effect transistor
112
from a subsequently formed conductive layer. The dielectric layer
114
can be a silicon oxide layer or a borophosphosilicate glass (BPSG) layer formed using, for example, chemical vapor deposition (CVD).
Next, as shown in
FIG. 1B
, the dielectric layer
114
is etched to form a contact opening
120
that exposes one of the source/drain regions
110
. Thereafter, conductive material such as tungsten is deposited, filling the contact opening
120
and covering the dielectric layer
114
to form a conductive layer
122
. The conductive layer
122
couples electrically with the source drain region
110
.
Next, as shown in
FIG. 1C
, a portion of the conductive layer
122
is removed to form a conductive plug
122
a
that couples electrically with the source/drain region
110
. In the subsequent step, another conductive layer is formed over the dielectric layer
114
, and the conductive layer is patterned to form a conductive layer
124
directly above the conductive plug
122
a.
Furthermore, another conductive layer
126
is formed above the alignment mark
106
.
The aforementioned method is capable of transferring the alignment mark
106
from the substrate
100
to the dielectric layer
114
and then from the dielectric layer to the conductive layer
126
. However, as the degree of integration for integrated circuit devices rises, the number of photoresist depositions and light exposure operations necessary for fabricating the devices will increase correspondingly. To minimize inaccuracy in pattern transfer resulting from a rugged dielectric surface, the dielectric layer
114
is usually planarized using a chemical-mechanical polishing method immediately after its is formed. In general, besides reducing processing difficulties in subsequent operation, planarization of the dielectric layer
114
is able to increase pattern transfer precision in photolithographic processes.
FIG. 2A
is a cross-sectional view showing the structure after the dielectric layer
114
in
FIG. 1A
is planarized.
After the dielectric layer
114
is planarized to form a dielectric layer
114
a,
a conductive plug
122
a
is formed within the planarized dielectric layer
114
a
as shown in
FIGS. 2B and 2C
. As shown in
FIG. 2B
, a conductive layer
123
is formed over the dielectric layer
114
a,
and then photolithographic and etching operations are conducted to pattern the conductive layer
123
. Consequently, a conductive layer
124
is formed that couples electrically with the conductive plug
122
a
as shown in FIG.
2
C. Because step height
170
of the alignment mark
106
is already lost after the planarization of the dielectric layer
114
a,
the conductive layer
123
that covers the planarized dielectric layer
114
a
does not have any step height markings for alignment. To provide the necessary alignment marks for subsequent process, a photoresist layer has to be deposited over the conductive layer
123
, and then photomask pattern has to be transferred to the photoresist layer. Finally, a portion of the conductive layer
123
above the alignment mark
106
is etched so that the alignment mark
106
reappears above the dielectric layer
114
a.
However, the above process of recovering lost alignment marks will increases the number of additional photomask-making and etching operations, thereby increasing production cost and manufacturing time.
In light of the foregoing, there is a need to provide a improved method of recovering the lost alignment mark above the dielectric layer.
SUMMARY OF THE INVENTION
Accordingly, the present invention is to provide a method for restoring the alignment mark on a substrate to the top of a dielectric layer after planarization. The method is capable of restoring the alignment mark on the substrate after the formation of a conductive plug and the planarization of the dielectric layer without additional photolithographic and etching operations. The restored alignment mark is formed on the upper surface of the planarized dielectric layer.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for restoring the alignment mark from the substrate to the top of a dielectric layer after planarization. The method includes the steps of forming a dielectric layer over a substrate, and then forming a cap layer over the dielectric layer. The cap layer fills the trench on the upper surface of the dielectric layer directly above the alignment mark and covers the surrounding trench region. Thereafter, a global planarization is carried out to remove the top portion of the cap layer. Finally, the remaining portion of the cap layer is removed so that an alignment mark re-emerges on top of the dielectric layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5786260 (1998-07-01), Jang et al.
patent: 5843600 (1998-12-01), Chu et al.
patent: 5904496 (1999-05-01), Richards et al.
patent: 5963816 (1999-10-01), Wang et al.
patent: 6015744 (2000-01-01), Tseng
patent: 6037236 (1998-07-01), Jang
Chu Chih-Hsun
Tseng Chin-Hung
Huang Jiawei
J. C. Patents
Umez-Eronini Lynette T.
United Microelectronics Corp.
Utech Benjamin L.
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