Electric lamp and discharge devices: systems – Plural power supplies – Plural cathode and/or anode load device
Reexamination Certificate
2002-08-22
2003-12-02
Wong, Don (Department: 2821)
Electric lamp and discharge devices: systems
Plural power supplies
Plural cathode and/or anode load device
C315S169400, C345S060000
Reexamination Certificate
active
06657397
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for resetting a plasma display panel, and more particularly, to a method for resetting the state of discharge cells of each of XY-electrode line pairs while a surface discharge type triode plasma display panel is driven by an address-while-display driving method.
2. Description of the Related Art
FIG. 1
shows the structure of a surface discharge type triode plasma display panel.
FIG. 2
shows an example of a discharge cell of the plasma display panel shown in FIG.
1
. Referring to
FIGS. 1 and 2
, address electrode lines A
1
, A
2
, . . . , A
m−1
, A
m
, dielectric layers
11
and
15
, Y-electrode lines Y
1
, . . . , Y
n
, X-electrode lines X
1
, . . . , X
n
, phosphor layers
16
, partition walls
17
, and a magnesium oxide (MgO) layer
12
as a protective layer are provided between front and rear glass substrates
10
and
13
of a general surface discharge plasma display panel
1
.
The address electrode lines A
1
through A
m
are formed on the front surface of the rear glass substrate
13
in a predetermined pattern. A rear dielectric layer
15
is formed on the entire surface of the rear glass substrate
13
having the address electrode lines A
1
through A
m
. The partition walls
17
are formed on the front surface of the rear dielectric layer
15
to be parallel to the address electrode lines A
1
through A
m
. These partition walls
17
define the discharge areas of respective discharge cells and serve to prevent cross talk between discharge cells. The phosphor layers
16
are deposited between partition walls
17
.
The X-electrode lines X
1
through X
n
and the Y-electrode lines Y
1
through Y
n
are formed on the rear surface of the front glass substrate
10
in a predetermined pattern to be orthogonal to the address electrode lines A
1
through A
m
. The respective intersections define discharge cells. Each of the X-electrode lines X
1
through X
n
is composed of a transparent electrode line X
na
(
FIG. 2
) formed of a transparent conductive material, e.g., indium tin oxide (ITO), and a metal electrode line X
nb
(
FIG. 2
) for increasing conductivity. Each of the Y-electrode lines Y
1
through Y
n
is composed of a transparent electrode line Y
na
(
FIG. 2
) formed of a transparent conductive material, e.g., ITO, and a metal electrode line Y
nb
(
FIG. 2
) for increasing conductivity. A front dielectric layer
11
is deposited on the entire rear surface of the front glass substrate
10
having the rear surfaces of the X-electrode lines X
1
through X
n
and the Y-electrode lines Y
1
through Y
n
. The protective layer
12
, e.g., a MgO layer, for protecting the panel
1
against a strong electrical field is deposited on the entire surface of the front dielectric layer
11
. A gas for forming plasma is hermetically sealed in a discharge space
14
.
FIG. 3
shows a typical address-display separation driving method with respect to Y-electrode lines of the plasma display panel shown in FIG.
1
. Referring to
FIG. 3
, to realize time-division gray scale display, a unit frame is divided into 8 subfields SF
1
through SF
8
. In addition, the individual subfields SF
1
through SF
8
are composed of address periods A
1
through A
8
, respectively, and display periods S
1
through S
8
, respectively.
During each of the address periods A
1
through A
8
, display data signals are applied to the address electrode lines A
1
through A
m
of
FIG. 1
, and simultaneously, a scan pulse is sequentially applied to the Y-electrode lines Y
1
through Y
n
. If a high-level display data signal is applied to some of the address electrode lines A
1
through A
m
while the scan pulse is applied, wall charges are induced from address discharge only in relevant discharge cells.
During each of the display periods S
1
through S
8
, a display discharge pulse is alternately applied to the Y-electrode lines Y
1
through Y
n
and the X-electrode lines X
1
through X
n
, thereby provoking display discharge in discharge cells in which wall charges are induced during each of the address periods A
1
through A
8
. Accordingly, the brightness of a plasma display panel is proportional to a total length of the display periods S
1
through S
8
in a unit frame. The total length of the display periods S
1
through S
8
in a unit frame is 255T (T is a unit time). Accordingly, including a case where the unit frame is not displayed, 256 gray scales can be displayed.
Here, the display period S
1
of the first subfield SF
1
is set to a time 1T corresponding to 2
0
. The display period S
2
of the second subfield SF
2
is set to a time 2T corresponding to 2
1
. The display period S
3
of the third subfield SF
3
is set to a time 4T corresponding to 2
2
. The display period S
4
of the fourth subfield SF
4
is set to a time 8T corresponding to 2
3
. The display period S
5
of the fifth subfield SF
5
is set to a time 16T corresponding to 2
4
. The display period S
6
of the sixth subfield SF
6
is set to a time 32T corresponding to 2
5
. The display period S
7
of the seventh subfield SF
7
is set to a time 64T corresponding to 2
6
. The display period S
8
of the eighth subfield SF
8
is set to a time 128T corresponding to 2
7
.
Accordingly, if a subfield to be displayed is appropriately selected from among 8 subfields, a total of 256 gray scales including a gray level of zero at which display is not performed in any subfield can be displayed.
According to the above-described address-display separation display method, the time domains of the respective subfields SF
1
through SF
8
are separated, so the time domains of respective address periods of the subfields SF
1
through SF
8
are separated, and the time domains of respective display periods of the subfields SF
1
through SF
8
are separated. Accordingly, during an address period, an XY-electrode line pair is kept waiting after being addressed until all of the other XY-electrode line pairs are addressed. Consequently, in each subfield, an address period increases, and a display period decreases. As a result, the brightness of light emitted from a plasma display panel decreases. A method proposed for overcoming this problem is an address-while-display driving method as shown in FIG.
4
.
FIG. 4
shows a typical address-while-display driving method with respect to the Y-electrode lines of the plasma display panel shown in FIG.
1
. Referring to
FIG. 4
, to realize time-division gray scale display, a unit frame is divided into 8 subfields SF
1
through SF
8
. Here, the subfields SF
1
through SF
8
overlap with respect to the Y-electrode lines Y
1
through Y
n
and constitute a unit frame. Since all of the subfields SF
1
through SF
8
exist at any time point, address time slots are set among display discharge pulses in order to perform each address step.
In each of the subfields SF
1
through SF
8
, a reset step, address step, and display discharge step are performed. A time allocated to each of the subfields SF
1
through SF
8
depends on a display discharge time corresponding to a gray scale. For example, when displaying 256 gray scales with 8-bit video data in units of frames, if a unit frame (usually, {fraction (1/60)} second) is composed of 256 unit times, the first subfield SF
1
driven according to video data of the least significant bit has 1 (2
0
) unit time, the second subfield SF
2
has 2 (2
1
) unit times, the third subfield SF
3
has 4 (2
2
) unit times, the fourth subfield SF
4
has 8 (2
3
) unit times, the fifth subfield SF
5
has 16 (2
4
) unit times, the sixth subfield SF
6
has 32 (2
5
) unit times, the seventh subfield SF
7
has 64 (2
6
) unit times, and the eighth subfield SF
8
driven according to video data of the most significant bit has 128 (2
7
) unit times. Since the sum of unit times allocated to the subfields SF
1
through SF
8
is 255, 255 gray scale display can be accomplished. If a gray scale having no display discharge in any subfield is included, 256 gray scale display can be accomplished.
FIG. 5
shows a typical d
Kang Kyoung-Ho
Kim Hee-Hwan
Lee Joo-Yul
Dinh Trinh Vo
McGuireWoods LLP
Samsung SDI & Co., Ltd.
Wong Don
LandOfFree
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