Method for repeated block timing analysis

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing

Reexamination Certificate

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C716S108000, C716S134000

Reexamination Certificate

active

07971168

ABSTRACT:
In various embodiments, each possible different instance of a repeated block can be concurrently optimized for timing. Each instance of a repeated block may be treated as a mode, such as a functional mode or testing mode, allowing implementation calculations to be performed simultaneously. Using multimode timing analysis, all instances of a repeated block can be analyzed and optimized simultaneously. Based on the multimode analysis, instances of a repeated block may be implemented identically or substantially similarly, which can reduce costs associated with implementing the same block more than once (e.g., impact to schedule, CPU/memory resources, ECOs).

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