Method for rendering usuable a defective raw programmable logic

Details Method for rendering usuable a defective raw programmable logic Method for rendering usuable a defective raw programmable logic

1987-10-27

1990-04-24

Arnold, Bruce Y.

Boots, shoes, and leggings

371 111, G06F 1120

Patent

active

049204971

ABSTRACT:
A method of rendering defective raw programmable logic arrays usable by locating the manufacturing defects within the raw logic array, reconfiguring the columns of a mask logic array, and mapping the mask logic array onto the raw logic array so as to mask the defects. A defective programmable logic array rendered usable by this method.

REFERENCES:
patent: 4698807 (1987-10-01), Marwood et al.
patent: 4722084 (1988-01-01), Morton
patent: 4751656 (1988-06-01), Conti et al.
Wey et al.; "On the Design of Fault--Tolerant Programmable Logic Arrays"; International Computer Symposium, Taiwan, R.C.C., (1986).
Kuo et al.; "Efficient Spare Allocation for Reconfigurable Arrays"; IEEE Design Test of Computers, pp. 24-31, Feb. 1987.
"Method to Reconfigure Logic Signal Paths"; IBM Technical Disclosure Bulletin; vol. 29, No. 4, Sep. 1986, pp. 1575-1578.
S. Upadhyaya and M. Demjanenko, "On the Repair of Defective field Programmable Logic Arrays to Increase Yield", ICCAD (Nov. 11, 1987).

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