Cleaning and liquid contact with solids – Processes – Including application of electrical radiant or wave energy...
Reexamination Certificate
2002-10-25
2004-09-07
El-Arini, Zeinab (Department: 1746)
Cleaning and liquid contact with solids
Processes
Including application of electrical radiant or wave energy...
C134S001000, C134S006000, C134S037000, C134S902000, C015S001520
Reexamination Certificate
active
06786222
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a method for removing particles from a semiconductor processing tool. The present invention is particularly applicable to processing tools used to fabricate semiconductor devices containing submicron design features, and to processing tools used in processing large diameter wafers, such as an eight (8) inch (200 mm) or twelve (12) inch (300 mm) wafers.
BACKGROUND OF THE INVENTION
In the fabrication of semiconductor devices, wafers are typically processed through a large number of different processing stations, including processing tools where the wafer is coated with resist or developed, as well as chemical vapor deposition (CVD), physical vapor deposition (PVD), implant, etch and lithography processing tools. As the wafers run through the different tools, particles which are present on the susceptors and other wafer handling equipment of the semiconductor processing tools can accumulate on the backsides of the wafers. Often, a high number of particles is found within such semiconductor processing tools.
Backside particles may cause problems in subsequent processing steps, including lithography or other imaging steps, where depth of focus is a critical issue. The particles on the backside of a wafer may cause the wafer to deform beyond the depth of focus as a vacuum is applied to the chuck holding the wafer. As a result, focus spots appear in the lithography step which contribute to reducing the process yield.
The problems associated with backside particles on semiconductor wafers become more pronounced as the design features of the fabricated semiconductor devices become smaller, and as the wafer being processed become larger. As the dimensions of conductive lines and interline spacings become less than about 0.25 &mgr;m, particularly less than about 0.2 &mgr;m, the ability of lithographic equipment to fulfill the stringent requirement with satisfactory accuracy in the presence of a large number of backside particles is increasingly reduced.
Additionally, serious problems arise for wafers with a large diameter such as 12 inch (300 mm) wafers. Due to the large size of the wafers the presence of backside particles results in an increased deformation and requires thus an increased clamping force in steppers.
While being most easily identified in lithography steps, backside particles may also cause problems in other processing steps. For example, particles may be transferred from one wafer to another, until they are transferred out of the initial processing tool into a processing tool that is sensitive to contamination, such as a diffusion furnace. Also, a nonuniform etch or deposition may arise in plasma processing steps due to temperature differences across the deformed wafer.
One prior art attempt to deal with the backside particle problem is disclosed in U.S. Pat. No. 5,780,204 to La et al. To improve the accuracy of photolithographic processing, La suggests to polish the backside of the wafers prior to the photolithography step by chemical-mechanical (CMP) polishing. Thereby a wafer backside with a suitable wafer flatness could be attained. However, for satisfactory results, this method requires that a polishing step on the wafer backside is performed for each processed wafer prior to each lithography step and particularly, subsequent to the deposition of a dielectric layer on the front side of the wafer. Thus a large number of polishing steps needs to be performed, especially if other processing steps which have problems with backside particles are to be treated in the same manner. Another disadvantage of frequent CMP polishing is that exposed films absorb moisture (H
2
O) from processing which degrades the properties of the film.
U.S. Pat. No. 5,966,635 to Hiatt et al. discloses another prior art attempt to solve the backside particle problem. Hiatt suggests that after coating a wafer with resist or after developing resist the wafer should be removed from the chuck, and the chuck be cleaned by dispensing a solvent such as EGMEA or PGMEA to improve precision and uniformity in subsequent operations. Further, a sponge which is at least partially saturated with a solvent may be moved across the chuck to remove particles.
In a further prior art solution, disclosed in WO 99/59201, it is suggested to use a smoother chuck with a surface finishing having a peak-to-valley roughness height with an average value of less than about 1000 Å, which reduces the particle formation during wafer loading or unloading. Such a specially designed chuck is more expensive than ordinary chucks and the highly polished surface is likely to become degraded over time by scratches and other surface damages.
In practice, wafers are often merely brushed clean before the lithography step.
A common cleaning method is to remove the particles from a semiconductor processing tool by cycling a large number of wafers (10 to 100 wafers) through the tool. A certain number of particles adheres to each cleaning wafer thereby reducing the number of particles remaining in the processing tool. However, this approach requires a large number of non-productive wafers used for cleaning purposes only, requires considerable storage capacity for the cleaning wafers and results in a significant down time of the tool.
Therefore, the present invention seeks to solve the above mentioned problems and shortcomings of the prior art and intends to provide an efficient method for removing particles from a semiconductor processing tool, thereby increasing the availability of the tool and reducing the nonproductive time required for cleaning. Further, the invention intends to provide an improved method for processing semiconductor wafers in which less effort and time needs to be directed to cleaning or removing backside particles from the process wafers, to increase the productivity and the yield of the manufacturing process.
REFERENCES:
patent: 5225000 (1993-07-01), Fujii et al.
patent: 6159421 (2000-12-01), Fujii
patent: 0790 642 (1997-08-01), None
Frisa Larry E.
Kellogg Scott S.
McEwan Grant W.
Montgomery Michael N.
Shahvandi Iraj Eric
El-Arini Zeinab
Motorola Inc.
Vo Kim-Marie
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