Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2006-01-13
2009-08-25
Coleman, W. David (Department: 2813)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S739000, C257SE21038, C257SE21626, C257SE21640
Reexamination Certificate
active
07579282
ABSTRACT:
A metal layer etch process deposits, patterns and anisotropically etches a polysilicon layer (24) down to an underlying metal layer (22) to form an etched polysilicon structure (54) with polymer layers (50, 52) formed on its sidewall surfaces. The polymer layer (50, 52) are removed to expose an additional surface area (60, 62) of the metal layer (22), and dielectric layers (80, 82) are formed on the sidewall surfaces of the etched polysilicon structure (54). Next, the metal layer (22) is plasma etched to form an etched metal layer (95) with substantially vertical sidewall surfaces (97, 99) by simultaneously charging the dielectric layers (80, 82) to change plasma ion trajectories near the dielectric layers (80, 82) so that plasma ions (92, 94) impact the sidewall surfaces (97, 99) in a more perpendicular angle to enhance etching of the sidewall surfaces (97, 99) of the etched metal layer (95).
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Adetutu Olubunmi O.
Luckowski Eric D.
Rauf Shahid
Ventzek Peter L. G.
Cannatti Michael Rocco
Coleman W. David
Freescale Semiconductor Inc.
Hamilton & Terrile LLP
Malek Maliheh
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